How are you modelling the on-die and on-package capacitance of the FPGA?
This email is subject to copyright and the information in it is
confidential. This e-mail, its content and any files transmitted with it
are intended solely for the addressee/s and may be legally privileged
and/or confidential. Access by any other person other than the addressee/s
is unauthorized without the express written permission of the sender. If
you have received this e-mail in error notify the sender immediately by
email, do not use the email or any attachment or disclose them to any
person, delete the email from your system and destroy all copies you may
have printed. Metamako LP does not guarantee that any email or attachment
is secure or free from viruses or other defects.
On 14 January 2016 at 16:57, Ramesh Ponnada <rameshp3note@xxxxxxxxx> wrote:
Hi All,
In my design I have high speed interfaces like DDR4 and PCIe 3.0 interface
operating at their maximum frequency.
I am also dealing with the PDN analysis for core voltage supplies on PCB
for Xilinx ultra-scale FPGA.
I would like to understand how important is it consider board level power
Supply Noise injected from voltage planes and its effects on SERDES
interface like PCIe 3.0 in my simulation.
Could you please let me know how can we model this noise as jitter to
perform channel simulation for eye diagram analysis..?
Thanks in advance..
Regards,
Ramesh Ponnada
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
