[SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling Guide
- From: "Hassan O. Ali" <hassan@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 13 Jan 2004 01:32:07 -0500
I'm afraid this discussion is getting into over-generalization and
over-simplification of the problem in question.
Chris Cheng says:
> if you have
> poorly design chip and package, you need a hell of a lot of decoupling and
> BC planes to fix it at the system level
That is one example of generalization. Not every device-level power
distribution flaw can be solved at the board level. As a matter of fact,
many papers/documents I've read so far on this subject do clearly
indicate the limitations of the PDS at the board level. The board-level
PDS design only focuses on providing the power quality at the device's
power pins/balls.
Contrary to what Chris Cheng wants us to believe, you cannot
realistically meet all power distribution requirements by focusing only
on the device level. For one thing, the power comes from outside the
device, right? How can you then ignore the path through which the power
goes through before entering the device! Will the power delivered
through two backplane connectors and a 60-in backplane trace be of the
same quality as that delivered through an inch of fat PCB trace?
Certainly not.
Hassan.
Scott McMorrow wrote:
>Chris is correct.
>
>This was exactly my point previously. Without knowledge of the silicon
>and package power distribution it is impossible to perform an analysis
>of the entire power distribution system. But a well designed piece of
>silicon and package will require very little support from the PCB.
>
>scott
>
>
>Chris Cheng wrote:
>
>
>
>>I disagree. No one should be surprised. I have said many times, there is
>>never a need for fancy decoupling scheme on PCB for properly design
>>processor and package. Nothing should be need for >100MHz core noise and
>>signal return is a case of reference plane management (does that sound like
>>a broken record yet ?)
>>
>>
>>
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