[SI-LIST] Re: Power Supply Distribution/Filtering/Decouplin g Guide
- From: steve weir <weirsp@xxxxxxxxxx>
- To: Chris.Cheng@xxxxxxxxxxxx, Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>,"'scott@xxxxxxxxxxxxx'" <scott@xxxxxxxxxxxxx>,Zhangkun <zhang_kun@xxxxxxxxxx>,
- Date: Thu, 08 Jan 2004 23:16:04 -0800
Chris, you won't find much disagreement here on the need to get the Si
right first, but there is this problem of controlling the Si vendors, and
there is also a certain amount of scale to watch out for. Eventually, we
are going to get into a corner where no amount of band-aids will work, and
maybe then all the Si vendors will get religion when people just can't use
their parts otherwise, but I think we are still far away from that point.
Steve.
At 07:46 PM 1/8/2004 -0800, Chris Cheng wrote:
>Band-aids and hemorrhaging are the correct descriptions here.
>I sat on both sides of the table (as a system designer and a semiconductor
>vendor) before and being a lazy person, I always find excuses to blame the
>other side :-D.
>Since I am now in a system house, I think the majority of decoupling work
>can/should be done at the Si/packaging level.
>I have long make the analogy that core power distribution is like a Japanese
>water fountain, you start with the smallest/fastest bucket/cap on chip, move
>on to medium size decoupling on package and end up with the slowest bulk on
>system. If you don't follow that, you will have more than a single problem
>in your hand. i.e. If you see >100MHz EMI radiating from your package, you
>will probably have a large >100MHz core power ripple on die. Instead of
>building a ground cage around your package or using thin core PCB, you are
>better off beating your Si vendor and have them bulk up their on die
>decoupling.
>Same on I/O power. Instead of multiple power planes for each I/O power or
>crazy BC PCB, make sure your I/O has enough on die decoupling and assume the
>pull up return current from gnd reference. Just make sure you have enough
>gnd via on your PCB and you are done.
>If you don't buy what I say, at least give me credit for being consistent.
>Read any threads I ever made in this forum dated back to the beginning and
>you will realize I sound like a broken record no matter whether the normal
>system speed at the time is 50MHz or 5GHz. And I practice what I preach,
>honest. No BC and nothing below .01uF on PCB.
>Simple and cheap.
>
>-----Original Message-----
>From: steve weir [mailto:weirsp@xxxxxxxxxx]
>Sent: Thursday, January 08, 2004 5:18 PM
>To: Chris.Cheng@xxxxxxxxxxxx; 'scott@xxxxxxxxxxxxx'; Zhangkun; silist
>Subject: Re: [SI-LIST] Re: Power Supply Distribution/Filtering/Decouplin
>g Guide
>
>
>Chris,
>
>I think the devil comes back to what we can control. I believe that in
>your work you have been able to influence the IC packaging sufficiently
>that best practices on signal / image have been closely followed. I think
>that has a huge demonstrated effect on system cost and performance.
>
>Part of the discussion is on ensuring that at chip-scale those practices
>are followed. Part of the discussion has been on quantitative evaluation
>of how well a design does before we build it. And part of the discussion
>has been on what band-aids can be applied to a poor package design that is
>hemorrhaging. In the long-run probably no amount of band-aids will work.
>
>I think the 100MHz number is low for a lot of cases. Somewhere north of
>400MHz, I agree, because of the inductive wall presented by the package
>interconnect. However, given the amount of single ended signaling above
>100MHz on high density boards, it can get pretty tough to image only one
>rail, and there is a lot of energy out there well above 100MHz.
>
>I also think that we need to be careful about any hard frequency
>limits. As we keep moving up the power curve, even low percentages of
>power become substantial absolute values.
>
>Regards,
>
>
>Steve.
>
>At 01:41 PM 1/8/2004 -0800, Chris Cheng wrote:
> >Scott, Steve, Zhangkun and friends,
> >I can appreciate the benefit of an optimized via pad for decoupling caps on
> >PCB, it certainly helps. I also can appreciate sophisticate power analysis
> >CAD tools for power distribution simulation.
> >However, I have done enough package and chip power distribution analysis
> >(both in Istvan's company and another processor company) that I believe a
> >properly designed chip/package does not need any core power decoupling
> >higher than 100MHz at the PCB level. I also believe that I/O power
> >distribution is a matter of image current/reference plane management rather
> >than how low your power plane or PCB cap impedance is.
> >So given the above assumptions, does all these via analysis or PCB plane
> >simulation tools matters at frequencies below 100MHz ?
> >Chris
> >
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