[SI-LIST] Re: Power Plane Noise Injection
- From: Iliya Zamek <i_zamek@xxxxxxxxx>
- To: Vijay Chachra <vijaychachra@xxxxxxxxxxx>, steve weir <weirsi@xxxxxxxxxx>, Mark Alexander <mark.alexander@xxxxxxxxxx>
- Date: Sat, 3 Sep 2011 11:37:36 -0700 (PDT)
Hello Vijay,
You are right that for the IO there are some specific in this noise generation
and impact on IO jitter.
We studied it in
http://www.altera.com/literature/cp/cp-01041-fpga-io-timing-variations-due-to-sso.pdf looking
at both, SSN and Power noise.
However, we have not considered such case as you described, when an external
aggressor placed on the same board. Planning this experiment it needs to take
into account that DUT resonance frequency for the external noise source will
not be the same as for the internal noise source.
It is pretty complex experiement; this correlate well with what Mark noted as
"specialized board".
Regards,
Iliya
From: Vijay Chachra <vijaychachra@xxxxxxxxxxx>
To: steve weir <weirsi@xxxxxxxxxx>; Mark Alexander <mark.alexander@xxxxxxxxxx>
Cc: si-list@xxxxxxxxxxxxx
Sent: Saturday, September 3, 2011 3:47 AM
Subject: [SI-LIST] Re: Power Plane Noise Injection
All,
Thanks for your detailed response.
Utilizing Block RAMs and other functional blocks for generating PRBS patterns
serves very well to characterize FPGA behavior when noise gets injected through
any of the sources.
My motivation to understand this was basically to study the effect of such
noise on IO circuits (part of DUT) especially in scenarios when all IOs
(operating at different voltage levels, with clock sources from different PLLs
from within the chip) toggle simultaneously in real time applications. I think
having an external FPGA based board as a generic test accessory with
flexibility to lengthen/shorten PRBS pattern lengths will serve the purpose
well.
Regards
Vijay
--- On Fri, 9/2/11, Mark Alexander <mark.alexander@xxxxxxxxxx> wrote:
From: Mark Alexander <mark.alexander@xxxxxxxxxx>
Subject: [SI-LIST] Re: Power Plane Noise Injection
To: "steve weir" <weirsi@xxxxxxxxxx>, "Vijay Chachra" <vijaychachra@xxxxxxxxxxx>
Cc: si-list@xxxxxxxxxxxxx
Date: Friday, September 2, 2011, 11:59 PM
Vijay,
In characterizing the power networks of Xilinx FPGAs we most often use
the DUT as the noise generator. We have had limited success with using
a second "noise generation" FPGA to generate and transmit noise to a
separate DUT victim FPGA, but this requires building a complex and
specialized board. Small isolated power networks (transceivers, PLLs,
etc.) have a high enough impedance that it's possible to drive noise
into them with a broadband power amplifier, but this doesn't work for
large core power systems.
When using the DUT as the noise generator (our primary approach), the
simplest thing to do is build a giant shift register out of most of the
device's flops, and shift a 1-0-1-0 pattern through it. Shifting PRBS
patterns with various toggle densities approximates the activity of
various datapaths and data types. By sweeping the clock frequency and
working with the size of the shift-register, most potential designs can
be approximated. Similar noise generators are built out of all major
resources: DSP blocks, BlockRAM and other functional blocks, to
characterize their noise generation potential.
Whether the intention is to characterize PDN noise or the performance
impact of such noise (clock jitter, etc.) dictates the choice of probe
type and capture method. Careful experiment design and hygiene is
obviously important (plenty of null tests, use of symmetry, attention to
metrics).
This kind of testing provides no end of useful and interesting
information, though it takes a surprising amount of time, effort, debug
and refinement.
Regards,
mark
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Thursday, September 01, 2011 10:08 PM
To: Vijay Chachra
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Plane Noise Injection
Vijay, I am sorry I don't know of any publications on this subject. I
only know what I have done in my own work.
Steve
On 9/1/2011 8:32 PM, Vijay Chachra wrote:
> Steve,
> As a follow-up question...Is there a reference available which I can
> refer to for understanding how programmable device can help in noise
> injection on power plane?
> Will a simple LFSR type design work as "good enough" noise injector or
> Are there other tried and tested designs available?
> Thanks
> Vijay
>
>
> --- On *Fri, 9/2/11, steve weir /<weirsi@xxxxxxxxxx>/* wrote:
>
>
> From: steve weir <weirsi@xxxxxxxxxx>
> Subject: [SI-LIST] Re: Power Plane Noise Injection
> To: si-list@xxxxxxxxxxxxx
> Date: Friday, September 2, 2011, 6:17 AM
>
> Jason, the issues at HF is coming up with enough raw power, and
> then a
> low enough impedance connection to the PDN. It is much easier to
> characterize devices on a purpose-built test PCB. A large
> CPLD/FPGA on
> the test PCB makes a good programmable noise generator.
>
> Steve.
> On 9/1/2011 2:21 PM, jason.pritchard@xxxxxxx
>
<http://us.mc1373.mail.yahoo.com/mc/compose?to=jason.pritchard@xxxxxxx>
> wrote:
> > Hi All,
> >
> > I have an application that I want to create noise on a power
> rail and determine the effects of that noise on a device.
> >
> > 1) What methods have people used to do this type of testing?
> > 2) If you use an RF transformer can you recommend a specific
> type/model that works effectively with the lower impedance of the
> power planes as a load?
> >
> > I would like to simulate DC-DC switching noise as well as high
> frequency noise.
> >
> > Any suggestions will be helpful.
> >
> > Thank-you,
> > Jason
> >
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> --
> Steve Weir
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Steve Weir
IPBLOX, LLC
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www.ipblox.com
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(707) 780-1951 Fax
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