[SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator)
- From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 19 Aug 2003 12:33:09 -0700
Larry,
I highly doubt providing a ground reference plane for signal return is
expensive. If the signals are in stripline configuration, all you need is a
single ground reference plane, the other side can be a different vdd plane
and the plane capacitance between the vdd/gnd will provide the return path
for the vdd side return current (provided ground via is presence whenever
the signal switch layer). Name me a single industrial high speed bus
(processors FSB, FCAL, Gb Ethernet etc) nowadays that doesn't mentioned the
requirement of proper reference plane in PCB and ground return via drill
when signal switch layer in their reference design. Name me one design in
your company that doesn't require correct high speed signal reference plane.
Finally name me one design that you have done that you intentionally
reference high speed microstrip traces with a difference VDD plane and you
end up using thin cores power planes and high speed caps on PCB to fix the
problem. Talk is cheap, put your money where your mouth is. Besides, I doubt
a thin core power/gnd plane pair will be a more cost effective way than
adding an extra layer to bury the microstrip signals that cannot be properly
referenced.
The on die I/O decoupling cap will provide the return current for io power
that is returned through the ground reference.
Unless you say high speed signal can only be run as microstrip that cannot
be reference to ground or you think striplines should not be at least
referenced to ground plane in one side, what you are saying is not valid.
-----Original Message-----
From: Larry Smith [mailto:larry.smith@xxxxxxx]
Sent: Tuesday, August 19, 2003 10:57 AM
To: Zhihui Wang
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass
Capacitor Caculator)
As Chris Cheng suggested earlier, a continuous ground path can help this
situation. But for system costs or other reasons, very few of us are
willing to have ALL of our return current on ground. If return current
ever gets onto a Vdd reference plane, it will inevitably have to jump planes
somewhere along the signal path. Certainly at the driver, return current
for a rising edge is on Vdd and for a falling edge is on ground. Return
currents at edge frequencies are going to have to go through a decoupling
capacitance somewhere. The same arguments can be made at terminating
resistors
located at the receiving end.
regards,
Larry Smith
Sun Microsystems
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
