[SI-LIST] Re: Power Integrity measurement equipment
- From: Heinrich.Smith <heinrich.smith2005@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 6 Apr 2006 23:15:23 +0800
Thanks to each guru's guidance.I got so much valuable information for me
solving pi relative problems.
Ultimetrix P4800 has good spec. but few technical application note on the
web.
I intend to purchase Agilent 4395A(10 Hz~500MHz).
10 Hz is capable for VRM or Bulk capacitor impedance measurement.
500MHz is enough for evaluating the decap solution on the PCB.
by the way,
APE cal. mode could calibrate the probe to its tip.
Does my comprehension make sense?
If i lose anything,feel free to supplement it with your comment.
After i reading some articles,i found Low frequency VRM impedance
measurement seems more complicated.
One is "Microprocessor Platform Impedance Characterization using VTT Tools"
proposed by Intel.
The other is proposed by SUN,Istvan Novak."Frequency-Domain
Power-Distribution Measurements ¡V An Overview"
I know the basic difference which one is to acquire time domain data and
then translate them into frequency domain,the other
(Istvan Novak's paper) provide a direct frequency domain mesurement by VNA.
I think these are two different approach but the same result.
Regards,
Heinrich.Smith
2006/3/30, Jim Antonellis <janton@xxxxxxxxxxxx>:
>
>
> Hi Istvan,
>
> Thanks for the clear insight to yet another pi mechanism that I for
> one had not considered. At the package level we have run resonance
> analysis, but NOT on the larger system PCBs, where the dimensions
> and stackups are ripe for many potential resonances.
>
> Regards,
> jim
>
>
> -
> Jim Antonellis janton@xxxxxxxxxxxx
> Broadcom Corp www.broadcom.com
> Office: 978.689.1669
> Cell: 978.618.4745
>
> This message and any attachments are Confidential and may be Legally
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>
>
>
> -----Original Message-----
> From: Istvan Novak [mailto:istvan.novak@xxxxxxx]
> Sent: Tuesday, March 28, 2006 9:26 PM
> To: janton@xxxxxxxxxxxx
> Cc: heinrich.smith2005@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: Power Integrity measurement equipment
>
>
> Jim,
>
> Very well said. Since you addressed the major aspects of the design
> process, I
> think it is worth mentioning that there are scenarios when the gradually
> decreasing
> bandwidth from chip to board needs further considerations, because
> otherwise
> unrelated supply rails get coupled:
> - take for instance a core supply. With a well-designed package and
> die, the
> board does not need to support very high frequencies; the board may become
> inductive at a few MHz. However, if clock leaks from the core, board
> resonances
> at the clock frequency or its harmonics may radiate excessively through
> the PCB
> - assigning reference planes in a proper way is very important. However,
> no
> matter how good job we do with a particular rail, in today's competitive
> designs
> we have many independent supply rails, supported by a number of planes in
> the stackup. Signal layers towards the bottom of the stackup will be
> reached by
> vias from the top, which vias will go through plane cavities towards the
> top. The
> vertical vias will excite those 'unrelated' top cavities. Closely
> spaced return
> vias, and/or differential signaling help, but will not make the problem
> go away
> completely.
>
> Regards,
> istvan
>
>
>
> Jim Antonellis wrote:
>
> >Hello Heinrich,
> >
> >I'm walking into the land of giants (the many pi experts who
> >have and continue to provide us all with great pi information)
> >but hopefully I have something to add... albeit at an apprentice
> >level.
> >
> >Yes, the IO buffers typically have their own power rail, Vddio,
> >seperate from the core power, Vddcore, but please keep in mind
> >that the return path, Vss, may be common at some level (package
> >and/or die)... I digress...
> >
> >I like to view the pi design as a multi-level problem with a
> >strict analysis order: die, pkg, pcb. My reasoning is this:
> >the input to stage (h+1(s)) is the output of the previous stage
> >(h(s)), or more simply, the "current profile" (di/dt) that the
> >pkg see from the die is certainly different than what the PCB
> >sees from the pkg. Hold on... I'm going somewhere with this
> >painfully obvious observation...
> >
> >Regardless of the root current source, core or IO buffer, the
> >die will have RLC effects that modify (H(s)) the source thereby
> >presenting a different current profile to the pkg. And, just
> >the same, the current profile that goes through the package
> >network will again modify such that the PCB will see another
> >yet different, lower frequency content profile... almost there...
> >
> >In the end, at the PCB, you will find that the package presents
> >a limiting inductance such that no matter what you do on the PCB,
> >you will never be able to satisfy a di/dt profile with components
> >above a certain package derived frequency. Of course the response
> >of any network is not so simple, but you may consider the pkg as
> >a LPF that limits the higher frequency components of the current
> >profile. Any PCB decoupling efforts above this frequency are
> >truely wasted (in regards to the task at hand).
> >
> >My pi strategy *ideally* has a different BW assigned to the
> >on-die decoupling, the package decoupling and the PCB decoupling,
> >the latter of which has lower frequency influenced by the VRM.
> >
> >In closing, consider what Istvan pointed out when he talked about
> >the horizontal inductance derived impedance, a temporal element
> >derived from a spatial mechanism, which screams: beware, lumped
> >vs distributed analysis!
> >
> >Jim
> >
> >-
> >Jim Antonellis janton@xxxxxxxxxxxx
> >Broadcom Corp www.broadcom.com
> >Office: 978.689.1669
> >Cell: 978.618.4745
> >
> >This message and any attachments are Confidential and may be Legally
> >Privileged. It is intended solely for the addressee. If you are not
> >the intended recipient, please delete this message from your system
> >and notify us immediately. Any dis-closure, copying, distribution or
> >action taken or omitted to be taken by an unintended recipient in
> >reliance on this message is prohibited and may be unlawful.
> >
> >
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx
> >[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Heinrich.Smith
> >Sent: Monday, March 27, 2006 11:37 AM
> >To: si-list@xxxxxxxxxxxxx; Istvan Novak
> >Subject: [SI-LIST] Re: Power Integrity measurement equipment
> >
> >
> >Thank you for your valuable introduction.
> >I still have some questions need your advice.
> >For modern IC design like CPU or FBDIMM architecture, the IO-buffer power
> >rail is different from core power rail,right?
> >Vio power rail has lower current driving but bringing higher frequency
> SSN
> >into PKG,PCB and , However,Vcore power rail has
> >higher current driving but the switching delta-I noise are enclosed
> inside
> >of IC(die).
> >>From your experience,
> >PCB's pi decap solution should cover to ?MHz for Vio power rail.(for
> >example,data rate 800MHz)
> > PCB's pi decap solution should cover to ?MHz for Vcore power rail.
> >In my experiments,the ESR of deacp above 100MHz will be large
> >increasingly,For example ESR:100mohm,that mean we need 100 capacitors to
> >drop the impedance to 1mohm,
> >My meaning is it is a hard work to drop the Z-impedance easily at hundred
> >MHz range,Who can cover this range's pi issue?
> >PKG's decap could solve it? or die-cap could solve it? or make an embeded
> >capacitor on PCB?
> >The second question,
> >When i measure Z-impedance of the power delivery network,Should i turn on
> >VRM?
> >If not necessary, The resonant frequency will be shifted before and after
> >turning on VRM,right? which result is important for me?
> >
> >Regards,
> >
> >-Heinrich.Smith
> >
> >
> >
> >2006/3/24, Istvan Novak <istvan.novak@xxxxxxx>:
> >
> >
> >>Heinrich,
> >>
> >>You need to start with the BW. The required instrument BW for power
> plane
> >>measurement depends on the excitation BW and maximum modal resonance
> >>frequency you want to care. If you know the signal rise/fall times
> >>hitting your
> >>planes, a simple BW=0.35/trise gives a good indication. The lowest
> >>parallel
> >>modal resonance frequency of a rectangular plane shape is F=1/(2*tpd)
> >>where tpd is the propagation delay along the longer side. Unless you
> have
> >>a very skinny narrow plane shape, the modal resonances usually blend
> into
> >>an inductive slope after the first few harmonics, so looking out to the
> >>tenth
> >>harmonic of the lowest modal parallel resonance is usually enough. For
> >>any
> >>power plane, if you are sure that you dont excite particular modal
> >>resonances,
> >>you dont need to worry about them, so you can take the smaller BW
> number
> >>of these two. You can plug in your numbers for each power rail, take the
> >>highest numbers you get and apply some safety cushion (at least an
> >>octave, 2x)
> >>to get the BW necessary for testing.
> >>
> >>In terms of VNA features, you need to make sure that the dynamic range
> >>is large
> >>enough if you plan on measuring mid to high-power systems, where the
> >>supply
> >>rail impedance is supposed to be low. At very low frequencies, when you
> >>want to measure the output impedance of DC-DC converters and/or
> >>large-capacitance and low-ESR bulk capacitors, you need to isolate the
> >>source and receive port returns, something that most VNAs dont offer
> >>today.
> >>Also, if you consider the entire frequency range that you need, which
> >>could
> >>range from Hz to GHz, you dont find any single instrument that would
> >>cover it.
> >>The same applies to cables and probes; those which are convenient for
> low
> >>frequency measurements are not optimum for GHz frequencies and vica
> versa.
> >>
> >>In terms of VNA model, you can check out the major VNA manufacturers:
> >>Agilent, Anritsu, Rohde Schwartz. You may also want to look at the VNA
> >>from
> >>Ultimetrix, which offers the DC blocking between input and output ports
> >>and
> >>an easy way to cascade VNAs to cover a wide frequency range.
> >>
> >>For more details you can check some of the posted papers on
> >>http://home.att.net/~istvan.novak/papers.html You can start with the
> >>two papers
> >>from DesignCon East 2003.
> >>
> >>Regards,
> >>
> >>Istvan Novak
> >>SUN Microsystems
> >>
> >>
> >>
> >>
> >>Heinrich.Smith wrote:
> >>
> >>
> >>
> >>>I would like to measure the power plane/capacitor impedance,Z.
> >>>I need which kind of VNA? how high BW?
> >>>which kind of the probe type? coaxial cable?
> >>>How to do the calibration?
> >>>Anyone could give me pictures or any documents ?
> >>>Thank you very much.
> >>>-Heinrich.smith
> >>>
> >>>
> >>>
>
>
>
>
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