[SI-LIST] Power Distribution Strategies
- From: otter30@xxxxxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 09 Jan 2008 17:14:59 +0000
Hello,
I am working on a pcb design which has 6 large ( >1000 pins ) ICs. Each IC has
its own set of
sequencing requirements, and so we are compelled to use lots of POL power
modules. All the
power modules accept a 12V input, and come in leadless packages (like BGAs with
out solder
balls) with 18 Vin pins.
In the first rev of the board, we tied all of these Vin pins to the main 12V
plane. This gives satis-
factory power distribution, but there is no way to measure the current drawn by
the modules or
to isolate any of them from the main 12V plane for troubleshooting.
I would like to tie the module Vin pins to a 12V island on the top layer of the
pcb, and have a large
current sense resistor tie the top layer island to the interior 12V plane layer
through multiple vias
(2 vias per amp?). This way I could measure the current drawn per module, and
identify problem areas. Problems could then be isolated by removing the sense
resistor.
How can I figure out if this is a feasible strategy? I know the output side of
the modules require a lo
impedance power delivery system (planes + bulk caps + decoupling caps) to the
ICs. This is perhaps
not as much of a concern on the input sides of the modules, since a switching
module with a 1.8/1.2V
output can tolerate lots of droop on a 12V input. But, I'm afraid of
inductively isolating the modules
so they can't source the dynamic current required by the ASICs/FPGAs.
My first thought is that using lots of bulk caps on the module inputs, a low
inductance package on the
sense resistor, and lots of vias from the internal 12V plane to the sense
resistor would help, but how
can I quantify this? What tools would I need to use to analyze this?
Any suggestions would be greatly appreciated.
Thanks,
Jim
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