[SI-LIST] Power Decoupling, again....

  • From: "Julian Ferry" <julian.ferry@xxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 23 Aug 2007 17:37:25 -0400

Sorry again for the double post. Still don't know what's causing the
problems.
 

 

 

 

Lars, 

 

Good questions. And to be honest, we don't have all the answers yet. 

 

I hope what follows doesn't come across as too much of an "advertorial",
but it's a complicated subject that I think requires some detailed
explanation. So if you might be offended by such ramblings, please tune
out now....

 

Our current efforts are focused on a few specific applications where the
POWER POSER will provide a "nearly" plug and play solution.  In these
applications, it's basically an off-the-shelf item, with no extra NRE
costs or development lead times.  

 

Of course, some engineering effort from system designers is still
required to properly implement a POWER POSER.  But such a design should
require much less effort from system designers than more traditional
approaches.

 

Additionally, we expect system engineers can often obtain an overall
cost reduction, AND a performance improvement with this approach.
Lowered costs are attributable to a reduction in high cost materials and
components, and improved performance is partly due to the fact that many
critical components are now located directly under the FPGA.

 

So from the perspectives of cost, time to market, and performance, the
standard products should look attractive in many applications.

 

With custom or semi-custom POWER POSERS, the equation changes a bit.  If
the new design is in the same family as an existing standard product,
then the NRE cost might range from $10-20K, and lead times of a month or
so to spin new boards and test.  The modular design approach has the
potential to save significant engineering effort for many applications.

 

For a completely new, "from scratch" application, of course the cost and
lead times are going to go up, and will probably be in the same ball
park as a traditional design.  But even in such applications, the board
space savings, localization of high cost materials, and potential
performance improvements might still make such an option attractive.    

 

Bottom line, the POWER POSER approach is not a complete drop in,
no-brainer, panacea solution (at least not yet!).  It is NOT going to
eliminate the need for intelligent power integrity engineering practices
and decision making. But we believe it is another tool you should
consider adding to your PI design toolbox, because in certain
applications, its use can make lot of sense.

 

 

Thanks for asking!

 

Julian Ferry

High Speed Engineering Manager

Samtec, Inc

 


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  • » [SI-LIST] Power Decoupling, again....