[SI-LIST] Re: Post Designcon thread
- From: Larry Smith <Larry.Smith@xxxxxxx>
- To: istvan.novak@xxxxxxx
- Date: Mon, 07 Feb 2005 09:14:46 -0800
Istvan - Yes, this seems like a good idea.
It seems that the major thrusts are: deep V, controled ESR caps, flat
impedance vs freq. Possibly there are others.
Would we restrict this to the capacitor range of frequencies or open
it up to "DC to daylight?" If so, we would have to deal with on-chip
and on-package capacitance and VRM performance.
There also is a distinction between cost performance consumer products
and big iron servers.
regards,
Larry
Istvan Novak wrote:
>
> Steve, Larry,
>
> The power distribution topic has been steadily growing at DesignCon.
> Ten years
> ago it was mentioned mostly in keynote speeches as a possible future
> problem.
> Today, we usually have two tracks and TecForums and panels dedicated to the
> subject. In the past years several aspects of the power distribution
> topic have
> appeared: low-power silicon design, component and PCB characteristics,
> measurement approaches and simulation results of various pieces of PDNs.
> Very little or none appeared so far on overall PDN methodologies; probably
> because this is a very wide-ranging and diverse topic itself, which may not
> easily fit into a 30-minute presentation. With a few basic approaches
> firming
> up in the industry, it may be time to discuss these possibilities in
> more detail at
> DesignCon. If you are interested, next year we could devote a half-day
> TecForum just to discuss power-distribution methodologies. Let me know if
> you are interested to participate/contribute.
>
> Best regards,
>
> Istvan
>
> Steve Weir wrote:
>
> >Jim, I had a blast at DesignCon, and want to thank everyone who attended my
> >paper.
> >
> >Larry and company's work on the subject of power delivery has led the way
> >for many of us. Introduction by SUN of the F^N method really got a lot of
> >people thinking about this issue.
> >
> >There are trade-offs to both methods, and Larry correctly pointed-out what
> >is one of the greatest strengths of the F^N method that he advocates,
> >against what may be considered the single greatest weakness of the big "V"
> >( single value capacitor ) that I advocate. I think it would be great to
> >air-out what both of these methods do and do not do, and then the informed
> >reader can use either method properly.
> >
> >Basically, what is at issue is the anti-resonance that occurs between the
> >apparent plane lumped capacitance and the discrete capacitor array in the
> >common case of boards that are not huge with high Er power dielectric. The
> >advantage that Larry sees to the F^N networks is that is loads the bypass
> >network with capacitors in the smallest values. Capacitor ESR depends on
> >the package size and the capacitance. So, the upshot is that for a given
> >closing frequency and impedance an F^N network has a higher resistance than
> >the big "V". Using Larry's 1mohm 100MHz 300pH example with 500pH 0603
> >capacitors I get an F^N network with roughly 150uohms versus about 60uohms
> >for the big "V". Consequently, plane skin effect aside, the AR Q with the
> >planes is about 2.5X times higher than with the F^N method. All thngs
> >considered equal, ( such as ignoring plane and at these extremely low
> >impedances even via skin effect ) this means the impedance peak at the AR
> >with the F^N method will be only about 40% that of the big "V".
> >
> >At this point, hopefully Larry will chime in if he feels I have gotten
> >anything wrong.
> >
> >My position is that both methods suffer large impedance departures due to
> >the AR. The salient questions are: what is the impact, and what can we do
> >about it?
> >
> >Assuming that the AR is well above the IC package power delivery cut-off,
> >the AR does not materially affect power quality to the IC die. What it can
> >affect is EMC from IC power, as even though the percentage power is way
> >down, substantial currents can still flow above the package cut-off. For
> >signals running in the offset stripline sandwich, the potential impact is
> >increased: signal crosstalk and EMI.
> >
> >How bad any of these problems are for either method is a matter of
> >coefficients. I consider the signal cross talk issue the more serious of
> >the problems. We can deal with that problem in two ways: First, reference
> >signals correctly so that we do not rely on the ancient CMOS power split at
> >the package / PCB boundary, and Second as necessary eliminate large Vcc
> >planes. The many voltages commonly needed often already do this to/for us
> >anyway.
> >
> >
> > Regards,
> >
> >
> >Steve
> >
> >
> >
> >
>
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