[SI-LIST] Re: Post Designcon thread
- From: Steve Weir <weirsi@xxxxxxxxxx>
- To: gtang@xxxxxxxx, <james.f.peterson@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 04 Feb 2005 15:39:28 -0800
George, thank you.
The AR occurs at different frequencies for different board geometries,
dielectric and capacitor arrangements. If it occurs below the IC package
LPF cut-off frequency, then we can have a real problem with power
delivery. There is risk of this when using large planes with thin, high Er
dielectric. I am going to put that circumstance aside for a moment, as a
"Don't go there!"
So assuming that the AR occurs well above the IC package LPF, the two big
concerns would be EMC, and signal return currents. This actually might be
a good opportunity to use Jon Powell's si-draw tool for the picture, but if
you have a copy of my paper, you can see where I show return current
transfer between the IC package and the PCB. What a nasty AR in the signal
frequency band does is place a big impedance discontinuity between the two
rails. So, we lose the ballasting that would normally balance return
current between the power rails.
How this isolation impacts the signals depends on how they were referenced
in the first place. This is Chris Cheng's favorite drum: If we reference
the signals to the same plane in both the IC package as on the board, then
the fact that plane impedance rises significantly compared to another has
very little impact on the return current of the signal. Imagine if you
will that we reference only to logic ground, and put a 10H choke in series
with the Vccio line. There will then be no high frequency return current
split back into the package. The signal return currents all appear on the
logic ground and only the logic ground interconnect. So long as within the
device we have adequate bypass across the rails, our signaling will work
quite well.
With CMOS we can pick either of the two power rails. And with the DDR2
standard, one was picked for data: logic ground, while the other was
picked for address and control, Vcc. So long as we don't mess up the
return current reference, this all can work quite well.
Now, if we want to address the EMC issues, the answer there is really to
drop the cavity size. Considering that a pedestrian signal today has a
100ps rise time, we have 3GHz plus components in ordinary signals. A 12x12
board in FR4, has a half-wave impedance peak in the 230MHz range. SMT
capacitors attached to planes through vias will not damp that bad boy out.
I will send you a dimensioned drawing after I return home this
weekend. What I would like from you is a stack-up so that I can see what
planes we are attaching to. Then, I can give you a little table that shows
the replacement ratio for a supply on each layer pair.
Page 14 of my paper includes a table of sample replacement ratios versus
0603 capacitors using 10 mil vias on 30 mil space for various plane
arrangements. If you are comparing against 0603 capacitors with 10 mil
vias on 50 mil space, then you will gain even a little more. The 30 mil
spacing was used to put the 0603s in the best possible light. The table
also shows what you can do with 0402s.
Regards,
Steve
At 01:45 PM 2/4/2005 -0800, George Tang wrote:
>Steve,
>Good presentation. I can see that you had a lot of fun, but I have a few
>questions if you don't mind.
>
>1. How do you plan to address the AR at ~300MHz if you have a large memory
>bank switching at ~300MHz, representing SSO drivers? How about at 400MHz,
>or 500MHz?
>
>2. Can you show how you would do the component and footprint via placement
>on the X2Y cap so you can replace 4 conventional caps with one X2Y cap?
>Let's say that the board thickness is 100mil, and the chip that needs
>decoupling is a large BGA. Keep in mind that you need to meet all the
>manufacturing requirements. What is the resulting inductance? For your
>convenience, I have attached the recommended footprint for the X2Y cap from
>the manufacturer web site at:
>
>http://www.johansondielectrics.com/products/surfacemount/x2y/JDI_X2Y_11-04.p
>df
>
>Draw the via placement and fill in the dimensions.
>
>Regards,
>
>George Tang
>LSI Logic Corp.
>
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Steve Weir
>Sent: Friday, February 04, 2005 10:49 AM
>To: james.f.peterson@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Post Designcon thread
>
>
>Jim, I had a blast at DesignCon, and want to thank everyone who attended my
>paper.
>
>Larry and company's work on the subject of power delivery has led the way
>for many of us. Introduction by SUN of the F^N method really got a lot of
>people thinking about this issue.
>
>There are trade-offs to both methods, and Larry correctly pointed-out what
>is one of the greatest strengths of the F^N method that he advocates,
>against what may be considered the single greatest weakness of the big "V"
>( single value capacitor ) that I advocate. I think it would be great to
>air-out what both of these methods do and do not do, and then the informed
>reader can use either method properly.
>
>Basically, what is at issue is the anti-resonance that occurs between the
>apparent plane lumped capacitance and the discrete capacitor array in the
>common case of boards that are not huge with high Er power dielectric. The
>advantage that Larry sees to the F^N networks is that is loads the bypass
>network with capacitors in the smallest values. Capacitor ESR depends on
>the package size and the capacitance. So, the upshot is that for a given
>closing frequency and impedance an F^N network has a higher resistance than
>the big "V". Using Larry's 1mohm 100MHz 300pH example with 500pH 0603
>capacitors I get an F^N network with roughly 150uohms versus about 60uohms
>for the big "V". Consequently, plane skin effect aside, the AR Q with the
>planes is about 2.5X times higher than with the F^N method. All thngs
>considered equal, ( such as ignoring plane and at these extremely low
>impedances even via skin effect ) this means the impedance peak at the AR
>with the F^N method will be only about 40% that of the big "V".
>
>At this point, hopefully Larry will chime in if he feels I have gotten
>anything wrong.
>
>My position is that both methods suffer large impedance departures due to
>the AR. The salient questions are: what is the impact, and what can we do
>about it?
>
>Assuming that the AR is well above the IC package power delivery cut-off,
>the AR does not materially affect power quality to the IC die. What it can
>affect is EMC from IC power, as even though the percentage power is way
>down, substantial currents can still flow above the package cut-off. For
>signals running in the offset stripline sandwich, the potential impact is
>increased: signal crosstalk and EMI.
>
>How bad any of these problems are for either method is a matter of
>coefficients. I consider the signal cross talk issue the more serious of
>the problems. We can deal with that problem in two ways: First, reference
>signals correctly so that we do not rely on the ancient CMOS power split at
>the package / PCB boundary, and Second as necessary eliminate large Vcc
>planes. The many voltages commonly needed often already do this to/for us
>anyway.
>
>
> Regards,
>
>
>Steve
>
>
>
>At 06:26 AM 2/4/2005 -0700, Peterson, James F (FL51) wrote:
> > I too enjoyed DesignCon and running into some people from the SI-list. I
> >actually was keeping an eye out for the infamous Chris Cheng, but never saw
> >him.
> >
> >It was interesting to see Larry Smith and Steve Weir spar over Steve's one
> >decoupling cap value only position. Too bad it had to end so quickly - it
> >was just getting interesting.
> >
> >I think an SI-List DesignCon get-together is a fantastic idea. We should
>try
> >to do this next year.
> >
> >Jim Peterson
> >Honeywell
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> >Behalf Of Chris Cheng
> >Sent: Thursday, February 03, 2005 8:03 PM
> >To: si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Post Designcon thread
> >
> >Sorry for wasting the bandwidth.
> >But its sure nice to put faces on people I only 'meet' in Si-list. Glad to
> >meet the new faces.
> >And for the old ones I know, it sure nice to know your grey hair has grown
> >just as much as mine. :-D.
> >Next time we should have a Si-list get together lunch instead of walking
> >around looking for strange faces ;-D. I'll bring the pie so those who feel
> >like it can throw at me.
> >I learned a few new things and refresh a few old ones.
> >Cheers.
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>-- Binary/unsupported file stripped by Ecartis --
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>-- File: x2y_footprint.bmp
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