[SI-LIST] Re: Post Designcon thread
- From: Larry SMITH <Larry.Smith@xxxxxxx>
- To: weirsi@xxxxxxxxxx
- Date: Fri, 04 Feb 2005 13:30:06 -0800
Steve - I also enjoyed DesignCon very much, especially the opportunity
to associate faces with names and renew old acquaintances. Thanks for
your comments below and yes, I believe you have accurately summarized
the major points concerning two different PDS methodologies: the big V
and flat impedance profile. Please allow me to further comment.
We are basically talking about the 300kH to 100MHz band of frequency
where ceramic capacitors are most important. One approach is to select
different values of capacitors with known ESR and combine them in
parallel to achieve a relatively flat impedance profile (resistive).
The number of capacitor values required depends on the ESR of the
capacitor and total ESL including mounting inductance. Up to a dozen
different capacitor part numbers may be required in this approach. The
big V method involves just one capacitor value and gives you a very deep
"V" in impedance with the minimum being far below the target impedance.
It is more convenient for manufacturing because fewer component part
numbers are required in assembly. The capacitor quantity is chosen to
make the PDS impedance below target impedance in the specified frequency
range.
I am a proponent of the flat impedance method for several reasons, the
most important is system damping. The flat impedance method absorbs
energy across a broad frequency range and turns it into heat. The big V
method has damping over a relatively small frequency range where it is
resistive. Capacitors in the capacitive or inductive regions do not
absorb energy but store it and then return it with a different phase.
This becomes important at both the high and low extremes of the ceramic
frequency range. At the low end, the VRM output impedance is similar to
an inductor. If a purely inductive slope crosses a purely capacitive
slope (VRM to big_V interface), a huge antiresonant peak will occur.
Similarly at high frequency, the pure capacitance of the power planes
crosses the pure inductance of the big V capacitors and forms a large
antiresonant peak. Both of these peaks are minimized using the flat
impedance method. The best way to manage the high frequency peak is by
maximizing your plane capacitance (thin dielectric and planes in
parallel) and extending the ceramic capacitor frequency by low mounting
inductance and small values.
For systems with relatively high target impedance (ie 20 mOhms) you can
eliminate many of the capacitor values in the flat impedance method and
the two methods begin to merge. There will be antiresonant peaks
between resonant dips but they can be kept below 20 mOhms. Tantalum bulk
capacitors with relatively high ESR can be used at the VRM to ceramic
interface to sit on top of the lower antiresonance. The upper
antiresonance may or may not hurt you depending on whether your circuits
are sensitive to it and the EMI properties of your system. Many viable
systems have been built using the big V method and it is hard to argue
with success.
In my experience, a well damped system is safer and more robust. You
can make changes to the stackup, change the clock frequencies and add
capacitors that target specific EMI frequencies without getting into too
much trouble. The big V method is a little more vulnerable to these
changes. I have always found that you can build a PDS with fewer
capacitors, less component cost and less board space by using the flat
impedance method, but you will have more part number complexity in
manufacturing and you need some CAD simulation to help you pick the
capacitors. I like the flat impedance method because it is more robust
and better optimized, particularly as we drive below 1 mOhm.
Thanks to all who participated in the stimulating discussions at
DesignCon and those who continue to contribute to SI-list.
regards,
Larry Smith
Sun Microsystems
Steve Weir wrote:
> Jim, I had a blast at DesignCon, and want to thank everyone who attended my
> paper.
>
> Larry and company's work on the subject of power delivery has led the way
> for many of us. Introduction by SUN of the F^N method really got a lot of
> people thinking about this issue.
>
> There are trade-offs to both methods, and Larry correctly pointed-out what
> is one of the greatest strengths of the F^N method that he advocates,
> against what may be considered the single greatest weakness of the big "V"
> ( single value capacitor ) that I advocate. I think it would be great to
> air-out what both of these methods do and do not do, and then the informed
> reader can use either method properly.
>
> Basically, what is at issue is the anti-resonance that occurs between the
> apparent plane lumped capacitance and the discrete capacitor array in the
> common case of boards that are not huge with high Er power dielectric. The
> advantage that Larry sees to the F^N networks is that is loads the bypass
> network with capacitors in the smallest values. Capacitor ESR depends on
> the package size and the capacitance. So, the upshot is that for a given
> closing frequency and impedance an F^N network has a higher resistance than
> the big "V". Using Larry's 1mohm 100MHz 300pH example with 500pH 0603
> capacitors I get an F^N network with roughly 150uohms versus about 60uohms
> for the big "V". Consequently, plane skin effect aside, the AR Q with the
> planes is about 2.5X times higher than with the F^N method. All thngs
> considered equal, ( such as ignoring plane and at these extremely low
> impedances even via skin effect ) this means the impedance peak at the AR
> with the F^N method will be only about 40% that of the big "V".
>
> At this point, hopefully Larry will chime in if he feels I have gotten
> anything wrong.
>
> My position is that both methods suffer large impedance departures due to
> the AR. The salient questions are: what is the impact, and what can we do
> about it?
>
> Assuming that the AR is well above the IC package power delivery cut-off,
> the AR does not materially affect power quality to the IC die. What it can
> affect is EMC from IC power, as even though the percentage power is way
> down, substantial currents can still flow above the package cut-off. For
> signals running in the offset stripline sandwich, the potential impact is
> increased: signal crosstalk and EMI.
>
> How bad any of these problems are for either method is a matter of
> coefficients. I consider the signal cross talk issue the more serious of
> the problems. We can deal with that problem in two ways: First, reference
> signals correctly so that we do not rely on the ancient CMOS power split at
> the package / PCB boundary, and Second as necessary eliminate large Vcc
> planes. The many voltages commonly needed often already do this to/for us
> anyway.
>
>
> Regards,
>
>
> Steve
>
>
>
> At 06:26 AM 2/4/2005 -0700, Peterson, James F (FL51) wrote:
>
>> I too enjoyed DesignCon and running into some people from the SI-list. I
>>actually was keeping an eye out for the infamous Chris Cheng, but never saw
>>him.
>>
>>It was interesting to see Larry Smith and Steve Weir spar over Steve's one
>>decoupling cap value only position. Too bad it had to end so quickly - it
>>was just getting interesting.
>>
>>I think an SI-List DesignCon get-together is a fantastic idea. We should try
>>to do this next year.
>>
>>Jim Peterson
>>Honeywell
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>>Behalf Of Chris Cheng
>>Sent: Thursday, February 03, 2005 8:03 PM
>>To: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Post Designcon thread
>>
>>Sorry for wasting the bandwidth.
>>But its sure nice to put faces on people I only 'meet' in Si-list. Glad to
>>meet the new faces.
>>And for the old ones I know, it sure nice to know your grey hair has grown
>>just as much as mine. :-D.
>>Next time we should have a Si-list get together lunch instead of walking
>>around looking for strange faces ;-D. I'll bring the pie so those who feel
>>like it can throw at me.
>>I learned a few new things and refresh a few old ones.
>>Cheers.
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>
>
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