[SI-LIST] Please check this spec. sheet!
- From: 송인명 <imsong@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 10 Feb 2004 21:42:34 +0900
Please check this spec. sheet!
P {margin-top:2px; font-size:10pt; margin-bottom:2px;}
Good morning!
Clock : [CPU] ---> [SDRAM] 90Mhz
Data : [CPU] <---> [SDRAM] synchronouse system by Clock.
(1). Clock's propagation delay measurement from CPU to SDRAM(using
Specctraquest)
Mode Delay
Switch rise Settle rise
Fast 0.40ns 0.50ns
Typ 0.42ns 0.55ns
Slow 0.35ns 0.69ns
* switch rise : First crossing time with Vilmax at rise edge.
* settle rise : Last crossing time with Vihmin at rise edge.
[Analysis : ONE]
● CPU to SDRAM (Write Operation)
Clock period : 11.11 ns
Tco_max : 4.9 ns
Tco_min : 1.3 ns
Setup time : 1.5 ns
Hold time : 0.8 ns
Jitter : 0.175 ns
Tclk_skew_setup : -0.35 ns
Tclk_skew_hold : -0.40 ns
① For Setup Time
T Flight_max <Clock_Period - Tco_max(Driver) - TSetup(Receiver)
- Tclk_skew_setup - Jitter
T Flight_max <11.11 - 4.9 - 1.5 -(-0.35) - 0.175
② For Hold Time
T Flight_min >Hold (Receiver) - Tco_min(Driver) + Tclk_skew_hold
T Flight_min >0.8 - 1.3 + (-0.40)
● SDRAM to ADSP (Read Operation)
Clock period : 11.11 ns
Tco_max : 6.0 ns
Tco_min : 3.0 ns
Setup time : 0.6 ns
Hold time : 1.8 ns
Jitter : 0.175 ns
Tclk_skew_setup : 0.69 ns
Tclk_skew_hold : 0.50 ns
① For Setup Time
T Flight_max <Clock_Period - Tco_max(Driver) - TSetup(Receiver)
- Tclk_skew_setup - Jitter
T Flight_max <11.11 - 6.0 - 0.6 -(0.69) - 0.175
② For Hold Time
T Flight_min >Hold (Receiver) - Tco_min(Driver) + Tclk_skew_hold
T Flight_min >1.8 - 3.0 + (0.50)
[Analysis : THE OTHER]
● CPU to SDRAM (Write Operation)
Clock period : 11.11 ns
Tco_max : 4.9 ns
Tco_min : 1.3 ns
Setup time : 1.5 ns
Hold time : 0.8 ns
Jitter : 0.175 ns
Tclk_skew_setup : 0.35 ns
Tclk_skew_hold : 0.50 ns
① For Setup Time
T Flight_max <Clock_Period - Tco_max(Driver) - TSetup(Receiver)
+ Tclk_skew_setup - Jitter
T Flight_max <11.11 - 4.9 - 1.5 + 0.35 - 0.175
② For Hold Time
T Flight_min >Hold (Receiver) - Tco_min(Driver) + Tclk_skew_hold
T Flight_min >0.8 - 1.3 + 0.50
● SDRAM to CPU (Read Operation)
Clock period : 11.11 ns
Tco_max : 6.0 ns
Tco_min : 3.0 ns
Setup time : 0.6 ns
Hold time : 1.8 ns
Jitter : 0.175 ns
Tclk_skew_setup : 0.69 ns
Tclk_skew_hold : 0.40 ns
① For Setup Time
T Flight_max <Clock_Period - Tco_max(Driver) - TSetup(Receiver)
- Tclk_skew_setup - Jitter
T Flight_max <11.11 - 6.0 - 0.6 -(0.69) - 0.175
② For Hold Time
T Flight_min >Hold (Receiver) - Tco_min(Driver) - Tclk_skew_hold
T Flight_min >1.8 - 3.0 - (0.40)
Question
1. Which analysis is right? (I think ONE is right, but someone doesn't)
2. Someone tell me I should use Switch delay rise too besides Settle delay
rise.
This means the hyteresis(Vihmin-Vihmax) can be zero. Is someone right?
If then, how much distortion is ocurred generally?
3. Is there any other analysis method in your fiedl?
Any reply will be OK to me!
Thanks a lot! ^___________^
Inmyung
[IMG]
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