[SI-LIST] Re: Placement of decoupling caps (UMR paper quote.)
- From: "Juergen Flamm" <jflamm@xxxxxxxxxxx>
- To: <Gareth.Baron@xxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 15 Apr 2004 18:40:25 -0700
Gareth,
Please consider a first order and simplified example assuming power
travels as fast as signals in a board, which is at about 0.14
meter/nanosecond.=20
Now assume a device switches at about 0.5 nanoseconds.=20
How far is your storage tank allowed to be away from the switching
device such that the needed power arrives in time to support the fast
switching time?
Considering this simplified first order model, it looks like that
capacitor location may matter.=20
Best Regards
=20
Juergen=20
-----Original Message-----
From: Gareth Baron [mailto:Gareth.Baron@xxxxxxx]=20
Sent: Thursday, April 15, 2004 6:10 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Placement of decoupling caps (UMR paper quote.)
May I add a maybe simplistic observation [and quite possibly incorrect]
=3D
?
Basically I see a capacitor as a current bin (storage tank).
Surely the further away a capacitor is from the source the further the
current has to travel. Assuming this path is resistive [power plane] =
=3D
then
the current is impeded. Hence will become less effective at decoupling
=3D
[ie
supplying the inrush current] as there is a resistance in the path.
Please feel free to correct me or explain why this concept may be =3D
incorrect.
I really want to understand the mechanisms at work here.
Gareth.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Charles Grasso
Sent: Thursday, April 15, 2004 5:36 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Placement of decoupling caps (UMR paper quote.)
On the issue of where the place your capacitors, a statement was made =
=3D
that a
paper from UMR proved that placement doesn't matter and a demand for
experimental evidence was also made. As is so often the case, however, =
=3D
there
is a qualifier. UMR showed that capacitor placement is not critical only
=3D
to
planes with a spacing of 10mils or less.
Perhaps more recent data might help.
Quote from the conclusion from a UMR paper published in the proceedings
=3D
of
the Y2K EMC Symposium, Washington DC.
Paper:Experimental Evaluation of Power Bus Decoupling on a 4-layer PCB
Authors: Chen,Xu, Hubing,Drewinak, VanDoren,Dubroff
ISBN: 0-7803-5677-2
Conclusion:the measured data in this paper demonstrates power bus =3D
decoupling
in a 4-layer PCB as a function of capacitor location. mutual inductance
plays an important role in power bus decoupling above the parallel =3D
resonant
frequencies of high-frequency decoupling capacitors. When the decoupling
capacitors and the IC are in close proximity, mutual inductance between
their vias encourages the active device to draw most of the transient
switching current from the nearest decoupling capacitor when switching.
Moving the decoupling capacitor closer to the active device increases =
=3D
the
effectiveness of the power bus decoupling. Therefore, in 4-layer boards
=3D
that
don't have closely spaced power/ground pairs, it is important to locate
=3D
the
decoupling caps near the ICs. Decoupling is maximized when the capacitor
=3D
via
that draws current from the farthest plane is located next to the IC =3D
power
or ground via that draws current from the farthest plane.
So placement DOES matter (apparently) for "high" impedance power planes.
=3D
And
is less critical for "low" impedance power planes.
Best Regards
Charles Grasso
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