[SI-LIST] Re: Pin vs. Die
- From: "Cuong Nguyen" <cuong@xxxxxxxxxxxxx>
- To: <romi.mayder@xxxxxxxxxx>, <conrad.herse@xxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 9 Jan 2015 09:33:01 -0800
In my opinion, one should NOT ignore the signaling at the pins and just focus
on the die because
the signals at the die are "better". At the pins, if you have non-monotonic
behaviors, overshoots,
undershoots, ringings, etc... these can have cumulative effects on the board
and components nearby.
The harmonics from these effects can worsen the board EMI and noise on the PDN.
I would look at
both pins and die pads but design to the pins. It's a choice one has to make.
Cuong
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Romi Mayder
Sent: Friday, January 09, 2015 9:28 AM
To: conrad.herse@xxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Pin vs. Die
Hi Conrad,
The issue of whether the IBIS simulation results show the signal at the pin or
the signal at the die as more or less or monotonic is strongly related to the
difference in the C_comp value (physically located at die) and the C_pkg value
used in the IBIS files. Many times the true SI differences are not as
significant as shown by IBIS transient simulation results. The issue is more
pronounced in two simulation cases, (1) when using big package sizes where the
C_pkg value may be large and (2) when using programmable logic devices where
the C_comp value may be large.
When running IBIS transient simulations for high speed memory applications, one
suggestion is to replace the RLC package model with a more accurate S-parameter
model of the package.
I hope this helps.
Kind Regards
Romi
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Conrad Herse
Sent: Thursday, January 08, 2015 12:04 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Pin vs. Die
Historically, when performing PCB SI (ibis) simulations I've always focused on
the SI quality of a signal when measured at the die of a receiving device, if a
signal needs to be monotonic I've ensured it's monotonic at the die rather than
at the pin. On (rare) occasions I've encountered instances where simulations
show a signal to have acceptable SI at the pin but not the die, for these cases
I've always worked to find improvements to achieve acceptable SI in the die
waveform.
Questions have been raised recently as to whether achieving good SI at the pin
of a device is adequate, without careful regard to the SI of a waveform at the
die. The rationale behind this being that datasheet specifications were
traditionally considered at the pin of a device. The reasoning goes that if
good SI is achieved at a device pin this meets the datasheet specifications and
no further improvements should be needed.
I personally do not subscribe to this line of reasoning but would be interested
in hearing feedback from others on this.
Thanks,
--
Conrad Herse
Alcatel-Lucent
Conrad.Herse@xxxxxxxxxxxxxxxxxx
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