[SI-LIST] Re: Phase jitter vs. period jitter

  • From: Vinu Arumugham <vinu@xxxxxxxxx>
  • To: jswarrier@xxxxxxxxx
  • Date: Thu, 24 Aug 2006 11:48:20 -0700

Jai,

You may want to verify if these vendors use JESD65 definitions for phase 
and period jitter.
http://www.jedec.org/download/search/jesd65b.pdf

Depending on your application, one or both types of jitter may be important.
Generally you have to account for phase jitter in serdes and common 
clock interfaces where each device has its own PLL.
For source synchronous interfaces you have to account for period jitter.
For some source synchronous interfaces like SPI4.2 that use dynamic 
alignment, you may have to account for both types of jitter.

Thanks,
Vinu

Jai Shanker wrote:

>Hello,
>
>I am evaluating 2 clock drivers for a project from
>different manufacturers and found that one specified
>phase jitter in ps, (RMS) and the other period jitter
>in ps, RMS. 
>
>The spec for phase jitter was not phase noise or in
>dBc/Hz. It helpfully adds that the cycle-cycle jitter
>on its input will equal the output, the part wont add
>jitter.
>
>I searched SI-list and couldnt find much info. Could
>somebody help provide some tips on how they compare/
>correlate.
>
>I did get some complex discussion involving
>convolution and integrals. If it can only be
>understood at that level (rather beyond me :-)) pls
>let me know. 
>
>I am now studying a Corning apnote on VCXO phase
>jitter  that is reasonably OK, but would appreciate
>any tips.
>
>Thanks & regards,
>Jai Shanker W.
>ACI Pvt Ltd
>
>
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