[SI-LIST] Paralleling driver outputs - is this still done?
- From: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 1 Apr 2004 11:38:23 -0700
Greetings:
I have a design that will (I believe) need to used a buffer for the clock.
The intent is to drive multiple loads from the driver. One concern is the
variable gate delays and the solution is to parallel the inputs and the
outputs.
Is this technique still used ? Does anyone have a feel for the long term
reliability of the device driven is such a way. The concern is that there
will be (for really short periods) a short between VCc and Gnd.
Thanks..
Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Email: charles.grasso@xxxxxxxxxxxx; <mailto:charles.grasso@xxxxxxxxxxxx;
%20>
Email Alternate: chasgrasso@xxxxxxxx <mailto:chasgrasso@xxxxxxxx>
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