[SI-LIST] Re: Paper on BGA crosstalk and power system

  • From: "Wei Zhou" <wzhou@xxxxxxxxxxx>
  • To: <Leonard.Dieguez@xxxxxxxxxx>
  • Date: Thu, 3 Mar 2005 09:28:37 -0800

Leonard,

The results seem to indicate the Altera IO pin cap is roughly half of
Xilinx. It would be interesting to see a comparison by setting Altera IO
with 4mA current strength vs Xilinx IO with 8mA current strength.

Wei

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Leonard Dieguez
Sent: Thursday, March 03, 2005 7:19 AM
Cc: SI List
Subject: [SI-LIST] Re: Paper on BGA crosstalk and power system

Cliford if you look at the Figures 14 ,16, 18 it clearly shows that the
sprial tests are both done with LVCMOS 4mA. Xilinx IO has an option to
use a

slew rate limited output "SLOW" and "FAST" which we selected "FAST" (no
slew

rate limiting) Altera does not have this option.  In the hammer test
BOTH
devices are changed to 8mA (Figure 19). That is pretty much as close as
you
can get. The rise times that are noticed in the Figure 20 (again both
devices at 8mA) could possibly be due to package layout differences and
output
capacitance differences of each device.

Leonard Dieguez
System IO Specialist

Clifford van Dyk wrote:

> Hi Mark
> A very interesting paper indeed. While not having seen the webcast, I
> assume that the content is more or less contained within the paper.
> While I do not see myself in the same league as other S.I. experts in
> the forum, hopefully my opinion is in some way useful. I would be
> interested to know the following:
>
> The final simulations show what looks to me like a 6 time greater
> crosstalk in the Altera package. This was done under the assumption
that
> di/dt was the same for both devices. The measured results (a ratio of
> 4.5:1) were made with the Altera drivers being significantly stronger
> than the Xilinx drivers. I would therefore have expected the simulated
> ratio to be less that 4.5:1, rather than the ca. 6:1 that seems to be
> indicated on figure 21. Why do you think this discrepancy exists?
>
> Also, it may have been more useful to perform the origional
measurements
> with equivalent drive strengths (measured risetimes, rather than "8mA"
> vs. "8mA fast", which was by your own admission, misleading) to get a
> more apples-to-apples measurement. Do you agree?
>
> Nevertheless, very interesting! Thank you for sharing.
>
> Kind regards,
> Clifford
>
> Mark Alexander wrote:
>
> >Hey all,
> >Some of you may have already attended this, but I wanted to draw your
> >attention to a WebCast seminar and accompanying paper that was
released
> >yesterday.  The topic is a joint study by Xilinx and SigCon (Howard
> >Johnson) of crosstalk and power system noise in FPGA systems.
> >
> >The paper:
> >http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf
> >
> >The archived WebCast (might not be available until tomorrow):
> >http://www.xilinx.com/events/webcasts/tol/01feb05.htm#3
> >
> >The WebCast is a full hour with Q&A at the end; the paper /seems
/long
> >but is actually pretty easy to read.  I especially like Howard's
> >explanation of the crosstalk model of power system noise and why it's
> >appropriate to the large BGA scenario.
> >
> >I'd be very interested to hear feedback from people on the list --
> >factors we didn't consider, overall usefulness of the information
> >presented, ideas for future studies on the same measurement platform.
> >
> >Thanks!
> >mark
> >
> >
> >
> >
> >
> >
>
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