[SI-LIST] Re: Package options/measurements for substrate noise reduction
- From: Tom Zimmerman <zimmerman@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 19 Apr 2002 08:19:45 -0500
In my experience, it depends on the wafer type. With epi wafers (very low
resistivity substrate), the bulk essentially acts as a low resistance
"ground plane" and prevents any on-chip substrate isolation structures
between digital and analog from being very effective. So for epi wafers,
we have found that the best approach is to conductively ground the backside
with as low an inductance as possible. In fact, in our application we used
a chip-on-board (no package) approach and used conductive epoxy to mount our
epi chips directly to the ground plane (very low inductance connection
between backside and board ground), and achieved excellent noise isolation
between analog and digital. So I suspect that if you have epi wafers and
you are not directly connecting the backside, your results will be less than
optimal. However, if you have non-epi wafers (higher resistivity
substrate), the optimal noise isolation strategy is different. In this
case, one can use on-chip guard rings, etc., to try to isolate the substrate
in the analog region from the substrate in the digital region. You would
then route the substrate and guard connections to system ground with minimum
inductance (might be good to bond them directly to the paddle if possible,
and if the paddle can be grounded with a low inductance connection), and it
doesn't matter so much whether the physical backside has a conductive
connection. Hope this helps,
Tom Zimmerman
Fermilab
> From: Yehuda Yizraeli <yehuday@xxxxxxxxxxxx>
> Subject: [SI-LIST] Package options/measurements for substrate noise
reduction
> Date: Thu, 18 Apr 2002 16:52:31 +0300
>
>
> Hi,
>
> Assuming we are putting our mixed signal chip into a package with solder
> mask on the paddle, namely the substrate will not be connected to ground
> (Its a mixed signal chip, analog and digital on the same die).
>
> 1) When looking at substrate noise and digital affecting analog circuit,
do
> you find this solution the most optimal
> 2) Does a conductive glue or a non conductive glue is the best option for
> separation?
> 3) Any idea of how to measure the difference (Apart from chip
functionality
> comparison).?
>
>
>
>
> thanks in advance, yehuda
>
>
>
>
>
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> Yehuda D. Yizraeli
> Mysticom LTD E-mail :
> yehuday@xxxxxxxxxxxx
> 1st HaZoran st, #6 Direct Tel: 972-9-8636-497
> P.O.B. 8364, Netanya 42504 Operator : 972-9-8636-465
> ISRAEL Cellular : 972-57-556-335
> Mirs : 18781*1
> Fax : 972-9-8636-466
> <http://www.mysticom.com>
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
