[SI-LIST] Re: PS decoupling for QFP and similars
- From: Michael_Greim@xxxxxxxx
- To: Larry.Smith@xxxxxxx, geoffrey.chacon.simon@xxxxxxxxx
- Date: Mon, 13 Oct 2003 08:40:11 -0500
Hi All,
Here is an interesting related email from
over a year ago, also from larry, that talks
a little about frequencies of interest vs
frequencies of influence for PDS design. I
was talking to this the other day and folks
found it illuminating so I thought that I would
add it to this thread.
best regards,
Michael Greim
----------------- Cut Here ---------------------
-----Original Message-----
From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
Sent: Wednesday, May 08, 2002 2:46 PM
To: si-list@xxxxxxxxxxxxx; sghsu55@xxxxxxxxxxxx
Subject: [SI-LIST] Re: Frequency criterion in power plane_Power
integrity
Sogo - the current transition time has a lot to do with inductance and
current magnitude. The governing equation is V = L*di/dt. Usually, we
do not want to see more than 5% voltage drop on our power rail and that
sets V in the above equation. L is a property of the packaging. The
core power path for a microprocessor might have 50pH loop inductance.
The current transient might be 50 amps from a 1 V supply. Now that we
have defined L, di and V, we can calculate the transition time, dt =
L*di/V = 50pH*50A/.05V=50nSec.
In other words, if we try to draw 50 amps out of a 50pH inductance in
less than 50 nSec, the voltage is going to droop more than 5% of 1V.
The GHz frequency associated with a 50nSec rise time is
0.35/50nSec=7MHz. This example has been for a microprocessor whose
core demands lots of current at a low voltage. The fast 50 amp current
transient simply is not going to make it out of the 50pH package
inductance.
Let's take another example of a 3.3V memory Dimm that draws 1 amp of
transient current. Perhaps the equivalent loop inductance for the Dimm
power supply is 1 nH. By the same calculation, dt =
1nH*1A/(3.3*.05)=6nSec. The frequency associated with 6nSec is
.35/6nSec=57MHz. In other words, the Dimm can draw power from the
mother board from DC up to 57 MHz. Above that frequency, the power
will have to come from onboard the Dimm.
Please note that these calculations assume that all current is in the
Vdd/Gnd loop. If signal return current gets involved, the problem is
much more complicated. A simple target impedance between Vdd and Gnd
is a good starting point, but SSN analysis involving Vdd, Gnd and
signals should be done after that.
regards,
Larry Smith
Sun Micorsystems
------------------ Cut Here --------------------
-----Original Message-----
From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
Sent: Friday, October 10, 2003 6:45 PM
To: geoffrey.chacon.simon@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: PS decoupling for QFP and similars
Geoffrey - You are asking some really good questions. There is a
corner frequency, above which there is very little you can do on the
PCB to improve the quality of the power as seen by the circuits on the
chip. That corner frequency is determined by the inductance of the
mounted package and the target impedance for the chip power supply.
It is easy to calculate a target impedance at either the chip or PCB
level. It is simply the tolerable noise voltage divided by the
transient current. If the circuits look out into the power
distribution system and see an impedance that is less than or equal to
the target impedance, they are happy.
The package and associated mounting structures form an inductance
which is in series with the PCB power supply as viewed from the chip.
The impedance of this inductance is j*omega*L. The corner frequency
occurs when the magnitude of the package impedance is equal to the
target impedance. Above that frequency, you could have an ideal zero
ohm power supply at the PCB level but still not be able to improve the
quality of power seen by the chip because of the package inductance.
Actually, it is best if the PCB presents a resistive impedance to the
package inductance equal to the target impedance well past the corner
frequency. This is because there is usually a low ESR capacitance
inside the chip that forms a parallel resonant circuit at the
chip/package resonant frequency.
If the PCB is inductive at chip/package resonance, it increases the Q
and forms an even higher impedance peak. If the PCB is resistive at
this frequency, it dampens the Q and lowers the impedance peak. The
circuits on the chip will see cleaner power when the Q is lower. It
is best if the impedance at the chip/package resonant frequency does
not exceed the target impedance, but this is often difficult. Very
few high powered chips in packages actually do this.
regards,
Larry Smith
Sun Microsystems
"Chacon Simon, Geoffrey" wrote:
>
> Hi people. I'm working with an FPGA and some other logic all in leaded
> packages. I was thinking about how can I provide a good decoupling, but
> I found myself with some existential thoughts. The first point I came
> with is that I can't decouple de PS beyond the limitations imposed by
> the lead inductance. I went to some IBIS models for the QFP and the
> inductance is about 10nH. Now, counting with 12 VCC pins then I may have
> an average 1nH inductance. So I thought how much effort I should put in
> thinking how to decouple this device if the voltage drop is already
> heavily affected by this inductance. At this point, I don't know if the
> device has embedded decoupling capacitors in the package, so I assume it
> doesn't. The manufacturer recommends to just estimate the required
> capacitance according to the power dissipated by the device, but he
> never considers the voltage drop due to the inherent inductance during
> the current spikes at the clock's edges.
>
>
> For low frequencies I assume the approach is correct since the
> inductance can be neglected. But what about for 150MHz frequencies and
> above? Or, maybe these packages aren't designed for such high
> frequencies, in which case I would have to move to BGA or smaller. And
> what about with the logic in TSSOPs and alike that has similar
> inductances (even lower) per pin?
>
>
>
> What I would like you to tell me is how much should I worry for
> decoupling such devices, and if for ~150MHz frequencies I definitely
> can't use QFP and TSSOPs. Any further recommendation is welcome. Thanks.
>
>
>
> geoffrey
>
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