Hi all, I am analyzing the output spectrum of a PLL + Serializer chip. Looking at the serial clock output I did see the locked output spectrum at 100Mhz. Second harmonic at 50Mhz and third harmonic 25Mhz. I do have a total of divided by 4 in the feedback path. In the other path the VCO output of 100Mhz are feed into a serializer block. Where is it also divided by 4 to get the low speed 25Mb/s parallel data to be serialized to the 100Mbs. Both the data and clock comes out and the spectrum frequency I have mentioned above are looking at the serial clock from the serializer. Here is my question, is there a way to find out where the 2nd and 3rd harmonic is coming from? Is it coming from the PLL feedback path or is it coming from the serializr divider? I can't use the spectrum analyzer to look at the inside the chip. I would like to find out a way to test and find out where the 2nd and 3rd harmonic is coming from in the chip. Any help is greatly appreciated. T. __________________________________________________ Do you Yahoo!? Yahoo! Platinum - Watch CBS' NCAA March Madness, live on your desktop! http://platinum.yahoo.com ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu