[SI-LIST] Re: PLL PPM Both positive and negative
- From: Tesla <emcesd@xxxxxxx>
- To: weirsi@xxxxxxxxxx
- Date: Thu, 20 Dec 2012 13:53:55 +0800 (CST)
Yes, it is true.
What is you oscillator, crystal,Mems or CMOS?
in oscillator, it is called short time stablity.
At 2012-12-20 03:11:07,"steve weir" <weirsi@xxxxxxxxxx> wrote:
>Several things can cause wander in a PLL. Power supply noise getting
>into the VCO is also a big cause of PLL headaches. It can be inherent
>to the type of phase detector used. And then there is always the
>possibility that your measurements are aliasing a measurement time base
>against the measured time base.
>
>Steve.
>On 12/19/2012 3:36 AM, vinod ah wrote:
>> Hi all,
>>
>> I am measuring a USB3 PLL clock for PPM. I see that the PLL is
>> generating clock with positive ppm few times and with negative ppm few
>> times.
>> Is it possible that same PLL can generate clock with positive ppm as
>> well as negative ppm assuming my temperature conditions are not
>> changing.
>>
>> The PLL is fed with a crystal clock of 12MHz and this crystal is
>> running with 12MHz - 10ppm. Since the temperature is not changing, the
>> crystal PPM is quite stable.
>> Also the same crystal is used for feeding multiple PLL's in the ASIC clock
>> tree.
>>
>> Regards
>> Vinod A H
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>
>
>--
>Steve Weir
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