[SI-LIST] Re: PI resonance test

  • From: "rpotluri ." <potluri.ravikumar@xxxxxxxxx>
  • To: Feng Wu <wufengthu@xxxxxxxxx>
  • Date: Tue, 21 Jan 2014 10:52:59 +0100

Hello SI/PI community people,
Could you please also give some suggestions on board PI/SI
characterization, especially PI issues. I would like to correlate all/some
of my simulations results with the lab measurements. Do you recommend to do
correlation with transient responses or frequency responses?. I cannot
foresee any issues and come up with a characterization plan.

@Cristian: I am extracting better S-Parameter models of power planes using
3D EM simulator for better noise simulations. Most of the circuity on my
board operated at 125MHz therefore I ensured using "Hyperlyynx" that PDN
impedance is strictly below the target impedance upto around 125MHz. At the
same time I am not totally satisfied with the simulation results keeping an
eye on the comment "it depends".

Best Regards,
Ravi

PS: Special thanks to the experts who have been helping with valuable
suggestions and discussions enabling to broaden the knowledge on SI and PI
issues.






On Tue, Jan 21, 2014 at 2:53 AM, Feng Wu <wufengthu@xxxxxxxxx> wrote:

> Hi Cristian
> I would provide you 3 cases where we need to handle PCB 600MHz or ever
> higher resonance.
> 1) for a low current consumption analog power rail of a chip, the target
> impedance is several ohms. the on-die decap is little. the PCB resonance
> really matter.
> 2) discrete circuit, such as DDR3 address bus flyby termination power. We
> need to carefully handle PCB resonance in 800MHz for DDR3-1600.
> 3) the power rail of RF PA  should not have any noise, at specific
> frequency band. From time domain power of view, this noise won't impact the
> voltage stability at all. you can't observe the noise by scope, but by a
> spectrum analyzer.
> You ever listed a lot of books from well-known expert. I would say they are
> correct, PCB only impact the performance below 100MHz,  while their
> pre-condition is
> 1) you are studying the power stability of a  chip
> 2) the chip has normal Cdie
> 3) the chip has normal package parasitic RLC.
> 4) the power rail requirement is normal.
> 5) the PCB stackup is also normal.
>
> as you can see, the example, which I provided in above, is different with
> the pre-condition.
> You may ask me what is the "normal". As mentioned by the others, the world
> of SI/PI is "it depends".
> Rule of thumb (guideline) is a good thing, and it is also not a good thing.
>
> Thanks
> Feng
>
> ----------
> Feng Wu (吴枫)
> Signal Integrity Engineer
> Cisco Shanghai
> ----------
>
>
> 2014/1/17 Cristian Filip <cris_filip2002@xxxxxxxx>
>
> > Hi Istvan,
> > I do agree with all that you said, but from a practical point of view
> that
> > means we should plot Z11 on every power rail at every location on the
> board
> > and add decoupling caps everywhere where resonances occur? How high in
> > frequency should we go? Steve hasn’t answered this question yet…
> > Thank you,
> > Cristian
> > BTW: I read most of your articles and I have your two books open on my
> > desk. As a matter of fact I do appreciate you very much for your
> > contribution to the SI/PI community.
> >
> >
> > ________________________________
> > From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
> > To: cris_filip2002@xxxxxxxx; "weirsi@xxxxxxxxxx" <weirsi@xxxxxxxxxx>
> > Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
> > Sent: Thursday, January 16, 2014 8:33:29 PM
> > Subject: [SI-LIST] Re: PI resonance test
> >
> >
> > Hi Chris,
> >
> > Any single-ended signal via, and to some lesser extent any differential
> > signal via, going through the cavity will excite it. Nearby return vias
> > will help to reduce the effect. More sinister excitation is the
> > potential high-frequency burst noise from vias connected to DC-DC
> > converters.
> >
> > Regards,
> >
> > Istvan Novak
> > Oracle
> >
> >
> > On 1/16/2014 8:07 PM, Cristian Filip wrote:
> > > Hi Steve,
> > > Could you please clarify here what is the excitation mechanism of the
> > cavity at 600 MHz? I would expect that the on-package and on-die
> capacitors
> > would suppress the high frequency content of the noise, so only low
> > frequency noise would reach the ports of the cavity.
> > > Thank you,
> > > Cristian
> > >
> > >
> > > ________________________________
> > > From: steve weir <weirsi@xxxxxxxxxx>
> > > To: Cristian Filip <cris_filip2002@xxxxxxxx>
> > > Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
> > > Sent: Wednesday, January 15, 2014 11:33:02 PM
> > > Subject: [SI-LIST] Re: PI resonance test
> > >
> > >
> > > Cristian, the problem is that the statements are both right and wrong
> > > simultaneously.  Those citations mostly refer to either the crossover
> of
> > > Xc of the cavity versus Xl of the discrete capacitor network, and / or
> > > the LPF between the power cavity and the IC die.
> > > Back at the power cavity, individual discrete bypass caps can exhibit
> > > practical mounted ESLs anywhere from around 100pH to 3nH or more.  Â
> > 3nH
> > > works out to about 12 Ohms @ 600MHz, but 100pH is only about 0.4 Ohms.Â
> > > Undamped cavity resonances can be many Ohms.  It only takes a few
> > > carefully chosen capacitors to damp resonances that could otherwise
> make
> > > nightmares for EMI and/or fast interfaces.
> > >
> > > The mantra of PI/SI is:Â  It depends.
> > >
> > > Steve.
> > >
> > > On 1/15/2014 4:46 PM, Cristian Filip wrote:
> > >> Hi Steve,
> > >> Thank you for replay. The upper limit of the frequency range where the
> > >> PCB and mounted MLCC are still effective is that kind of information
> > >> that shows up on nearly every PI book or article. Although there are
> > >> variations from one author to the other most of them agree on
> > >> 80/100MHz. Here are few examples:
> > >> 1.Dr. Eric Bogatin, “Signal and Power Integrity Simplifiedâ€, 
> > >> Second
> > >> Edition, page 632
> > >>
> >
> ------------------------------------------------------------------------------------------------------------
> > >> TIPThe frequency region that board level PDN design can influence is
> > >> roughly from the 100 kHz range up to about 100 MHz. This is where the
> > >> planes of the board and the multilayer ceramic capacitors (MLCC) can
> > >> play a role.
> > >>
> >
> ------------------------------------------------------------------------------------------------------------
> > >> 2.Vishram S. Pandit, Woong Hwan Ryu, Myoung Joon Choi, “Power
> > >> Integrity for I/O Interfaces: With Signal Integrity/Power Integrity
> > >> Co-Designâ€, page 148 and Figure 5.19
> > >>
> >
> ------------------------------------------------------------------------------------------------------------
> > >> The effective frequency range of the board ceramic (edge) capacitor is
> > >> from 1 MHz to tens of MHz, and the package capacitor is from tens of
> > >> MHz to a few hundreds MHz. The chip capacitor can be effective all the
> > >> way to a very high frequency range.
> > >>
> >
> ------------------------------------------------------------------------------------------------------------
> > >> 3.Madhavan Swaminathan, A. Ege Engin, “Power Integrity Modeling and
> > >> Design for Semiconductors and Systemsâ€, please see Figure 1-40 at
> page
> > >> 65 and the explanation at page 64
> > >>
> >
> ------------------------------------------------------------------------------------------------------------
> > >> Between 10 and 100 MHz, the interaction between the package and board
> > >> becomes important.
> > >>
> >
> ------------------------------------------------------------------------------------------------------------
> > >> You seem to disagree with all of those authors, so could you please
> > >> provide us your number along with explanations? Is this number typical
> > >> for most of the industry designs or it is just the result of an
> > >> experimental prototype meant to push the technology towards its
> limits?
> > >> Thank you,
> > >> Cristian
> > >>
> > >> *From:* steve weir <weirsi@xxxxxxxxxx>
> > >> *To:* si-list@xxxxxxxxxxxxx
> > >> *Sent:* Tuesday, January 14, 2014 9:05:45 PM
> > >> *Subject:* [SI-LIST] Re: PI resonance test
> > >>
> > >> Cristian, 600MHz is still a low enough frequency that capacitors can
> > >> usually be used to damp PDN resonance, especially if the power cavity
> is
> > >> close to the same PCB surface as the capacitors.
> > >>
> > >> Steve.
> > >> On 1/14/2014 4:16 PM, Cristian Filip wrote:
> > >>> Hi Ravi,
> > >>> As I know that you are using HyperLynx for PDN characterization, I
> > >> want to remind you that the simulator is not accounting for the
> > >> on-package and on-die capacitance, or for the package inductance.
> > >> Consequently the resonance that you see on your plot is not what the
> > >> IC power pins will see. The 600 MHz frequency resonance is quite high
> > >> and the capacitors mounted on the PCB are not effective due to the
> > >> loop inductance. This being said you should either be worried only
> > >> about resonances that occur at lower frequencies (typically less than
> > >> 100 MHz) or even better, perform transient simulations that include
> > >> beside the PCB PDN, power aware models (IBIS 5.0 or newer, Spice,
> CPM).
> > >>> Cheers,
> > >>> Cristian
> > >>> Â
> > >>> ________________________________
> > >>> From: çŽ‹ç´ åŽ <star_wang1@xxxxxxxxxxx <mailto:
> > star_wang1@xxxxxxxxxxx>>
> > >>> To: si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx>
> > >>> Sent: Tuesday, January 14, 2014 7:37:45 AM
> > >>> Subject: [SI-LIST] PI resonance test
> > >>>
> > >>>
> > >>> Dear all
> > >>>   I have a problem about how to test power plane resonance.
> > >>>
> > >>> I did a simulation of a 1.0v power plane(12v turn 1.0v) and the
> > >> resonance is
> > >>> high at 600mhz,how can I verify my simulation through test?
> > >>>
> > >>> Thanks
> > >>>
> > >>>
> > >>>
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> > >> --
> > >> Steve Weir
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