[SI-LIST] Re: PI- filter for power filtering

  • From: "Dagostino, Tom" <tom_dagostino@xxxxxxxxxxx>
  • To: "'whizplayer@xxxxxxxxx'" <whizplayer@xxxxxxxxx>,si_list <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 31 Oct 2001 16:35:20 -0800

If the filter is a Pi then you need to ask another question, how well does the 
filter keep noise from the load localized and not polluting other loads.

Tom Dagostino
Modeling Manager
Mentor Graphics Corp.
SAE
tom_dagostino@xxxxxxxxxx
503-685-1613


-----Original Message-----
From: Bob Patel [mailto:whizplayer@xxxxxxxxx]
Sent: Wednesday, October 31, 2001 3:44 PM
To: si_list
Subject: [SI-LIST] PI- filter for power filtering



Hi! Gurus, In a lot of designs that I have come across
in various designs the implementation of PI filters
i.e. capacitor-->Ferrite bead-->capacitor for
filtering power to the concerned pins.
Now, since it is tough to put fat traces from these
filters to the internal BGA pins, small power islands
are used. The ferrite bead straddles this island. With
this approach you end up cutting up the power plane
and thus lose some routing space on the adjacent
signal layer.
My question if anybody has some measured or simulated
data as to how much noise reduction is achieved by
this approach rather than using a solid plane. Keep in
mind I am talking about just one power say 3.3V and
using this approach to reduce the noise or to say
"clean power " to the chip.
If ferrite beads are used then how effective it is
over a frequency range?
Thanks in advance
Bob

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