[SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance?
- From: Steve Lund <slund@xxxxxxxxxx>
- To: "Signal Integrity Listserv (E-mail)" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 24 Feb 2003 15:14:46 -0600
Si Gurus,
Thanks for your input to my questions. Here is a re-cap of the answers.
Please correct me if I misunderstood.
1. Via-in-pad has issues with manufacturing unless the via is small diameter
(10 mils). Via-beside-pad would be a good alternative if the prior was
unavailable or too expensive. It looks like I'm off to check with our board
house as to which they prefer.
2. Thermals should be eliminated from the plane connections for SMT
components.
3. You can't get there from here with a 4 layer stackup. It looks like we
live without a little extra plane capacitance.
Regards,
Steve
> -----Original Message-----
> From: Steve Lund [mailto:slund@xxxxxxxxxx]
> Sent: Friday, February 21, 2003 5:10 PM
> To: Signal Integrity Listserv (E-mail)
> Subject: [SI-LIST] PDS Capacitor Mounting Details for Lowest
> Inductance?
>
>
>
> Si Gurus,
>
> This subject has been discussed at length on this list and I
> agree on the
> need to minimize the mounted capacitor inductance but have a
> few questions
> regarding the actual application. Befor I get started please
> realize that I
> am a circuit designer with limited knowledge about actual PCB
> design. So far
> most of our designs fit on standard 4 layer PCBs (signals on
> the outside and
> power and ground in the middle).
>
> 1. Is it possible to do via-in-pad (prefered) or
> via-next-to-pad without
> incurring extra cost or manufacturability penalties? At one
> time I believe
> that one of our vendors didn't like this approach for a
> reason that I don't
> remember. What is the current thinking on this approach among PCB
> manufacturers?
>
> 2. What about thermal reliefs for the connections to the
> internal power and
> ground layers? These originated for solderability reasons on
> through-hole
> boards. Are they still required on SMT mounted bypass caps? I
> know that
> these are not wanted due to the increase in mounting
> inductance that they
> cause. Is it possible to get rid of these without incurring
> manufacturability problems? If not is there a recommended geometry?
>
> 3. Does anyone have a prefered stack up for 4 layer .062"
> boards? I would
> like to have as much plane capacitance as possible. For high plane
> capacitance you need close pwr-gnd plane spacing but this
> then leads to
> large spacing over planes for the signal layers. Added to
> this is the fact
> that needed dielectric layers are only available in certain
> standard sizes.
> Does anyone have any recommendation for a compromise stack-up
> that would
> work good for these conditions?
>
> If would also appreciate any links that you could give me
> where I could
> learn more about the practical aspects of implementing this
> PDS strategy in
> a PCB. It would also make it easier to send known good
> information to our
> PCB designer.
>
>
> Thanks for your thoughts,
>
> Steve
>
> Steve Lund
> Sr. Design Engineer
> OPW Fuel Management Systems
> 114-300 Mackenan Dr.
> Cary, NC 27511
> (919)460-6000 x2133
> (919)460-7595 FAX
>
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