[SI-LIST] Re: PDN sim: why not IFFT ?
- From: "O'Brien, Michael" <Michael.OBrien@xxxxxxx>
- To: "i_zamek@xxxxxxxxx" <i_zamek@xxxxxxxxx>, "hreidmarkailen@xxxxxxxxx" <hreidmarkailen@xxxxxxxxx>
- Date: Wed, 7 Aug 2013 09:00:36 -0600
The paper listed below covers core PDN analysis. Does anyone know if this
technique can or has been used for SerDes power supply PDN of an ASIC?
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Iliya Zamek
Sent: Tuesday, August 06, 2013 10:29 AM
To: hreidmarkailen@xxxxxxxxx
Cc: si-list; istvan.novak@xxxxxxxxxxx
Subject: [SI-LIST] Re: PDN sim: why not IFFT ?
Agathon,
You asked: "Please, somebody explain why I never see this in the literature...".
We used the IFFT approach to the PDN analysis and presented it at Designcon
2008:
http://application-notes.digchip.com/038/38-21432.pdf.
In this work the Dynamic current inside the chip was modeled. In order to
evaluate if modeling was correct we did simulations and measurements of PCB
power plane' noise that origin of toggling on-chip logic. The correlation
between simulations and measurements noise' waveforms and spectrums was
surprisingly good.
In experiments the external power supplies and evaluation PCB were used. As
Istvan pointed out, using VRM and including it into the model might make
analysis more complicated.
If you have any questions, please, feel free ask me offline.
Thank you.
Iliya
________________________________
From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
To: hreidmarkailen@xxxxxxxxx
Cc: si-list <si-list@xxxxxxxxxxxxx>
Sent: Monday, August 5, 2013 6:17 AM
Subject: [SI-LIST] Re: PDN sim: why not IFFT ?
Hello Agathon,
Regarding LTI, I referred to the PDN, not its model. Our real-world components
are causal and (with the exception of active devices, like VRM) passive, so it
is not important to mention that requirement because it is guaranteed by nature.
Of course the corresponding models also need to be passive and causal, but the
comment was about the PDN itself, not the model. Linearity and time invariance
on the other hand is not necessarily true for PDN circuits. As Larry pointed
out, VRMs are inherently nonlinear in their operation, and though from outside
an averaged linear model is many times adequate, it is not necessarily
adequate under all conditions. Similarly, time invariance may show up in the
response:
for instance, a thermally unstable DC-DC converter may show significant changes
in their response as they heat up or cool down, and it can happen so quickly
that changes the impedance profile when measured with a slow sweep in the
frequency domain. In such cases uses IFFT to get the time-domain response
would be misleading.
Regarding PCB/VRM response and stimulus length: with a dominant die-package
resonance the short step-response trace may capture most of the data signature
you need, but the stead state is not captured properly. As always, it depends
whether this approximate solution is sufficient for your purposes or not.
Regards,
Istvan Novak
Oracle
On 7/17/2013 6:19 PM, agathon wrote:
> Istvan,
> Thanks very much. At least, now I know I'm not down the rabbit hole.
> All my models are of passives, including die which is just
> interconnect, and so LTI.
> You say "...linear and time invariant ..." (LTI) ... Instead, don't
> you mean causal for passives models? You have a paper or two on this.
>
> * Also, my stimulus is die side & steady state (enforced) only, dc
> suppressed & start is windowed, in the form of a PWL file, extracted
> from actual die ckt with std flow. Avg of data record = 0. As a
> result, I can read the wc bump noise as simply the neg. peak in the sim
> result.
>
> * The dc drop is totally separate; handled differently. I don't use a
> vrm dc source. I gnd the vrm end, again because I want steady state,
> in order to help with the approach taken. My result is die Vnoise
> (steady state) at bumps.
>
> * Further, the vrm and all other pcb noise sources I segregate into a
> different problem; I'm dealing with die only impact at bumps (with pcb
> model included & all pkg/pcb dcaps). The pcb sources can be done in a sep.
> sim and added in to the budget (by LTI). It's a different animal
> altogether. I don't include any pcb filters for ext. noise, like
> inductors or ferrites; they're part of ext. noise filtering.
>
> * Additionally, a vrm dc step does nothing but show how substrates &
> passives respond to a the supply's step; irrelevant to me for die bump
> considerations. A vrm also introduces big headaches requiring use of
> initial conditions to get the sim stable @ that step (even if smooth),
> since it by definition injects current ramps as initial operating
> condition
> (V=L*di/dt) that aren't "real" for my simulation. Likewise, any die
> current stim ramps induce V steps. Avoiding init conditions and ext.
> step sources also means I help avoid the low freq. minefields in models.
>
> * So, I need a huge stimulus length to cover the freq. range and a
> huge # of points, but I'm not dealing with the deep low freq of pcb
> noise sources here.
>
> * The die stimulus is based on a PRBS just long enough to cover the
> total sim time (1-3+ usec). Bad choice to concatenate shorter PRBS;
> you get harmonics at the PRBS period. Tradeoff is that the longer
> PRBS gives you longer run-lengths, so less hi-freq energy. Looking
> into causal notch filter with the concat method to attenuate the harmonics.
>
> Waddya think?
>
>
> On Tue, Jul 16, 2013 at 9:20 AM, Istvan Novak <istvan.novak@xxxxxxxxxxx>wrote:
>
>> Hello Agathon,
>>
>> Theoretically there is nothing wrong with the process. Practical
>> details may make a generic implementation challenging. We need to
>> assume that the entire PDN is linear and time invariant and in this
>> case (from power source to bump), this means not only the capacitors
>> and the DC source, but also the silicon. Another practical challenge
>> is the very wide relative bandwidth: DC sources may have signatures
>> in the kHz frequency range, the package and silicon have features in
>> the GHz frequency range. The usual FFT processes require equidistant
>> spacing of samples, which can result in millions of points to
>> transform. Doable today, but just a little while back this was a
>> major hurdle. And there is the uncertainty of the excitation
>> waveform. When people do the same process in signal integrity, the
>> signal is much better known; with PDN noise generated by the silicon,
>> many users would be left to wild speculations.
>>
>> Best regards,
>>
>> Istvan Novak
>> Oracle
>>
>>
>>
>> On 7/16/2013 2:33 AM, agathon wrote:
>>
>>> Hello all,
>>> For obtaining a time domain response at IC bumps, V(t), given the
>>> die current stimulus I(t) which is already assured to be steady
>>> state itself in a single record, not a repeated concatenation with a
>>> constant moving avg., then dc suppressed, the following seems
>>> straightforward:
>>>
>>> 1. Convert stimulus I(t) to the freq. domain with FFT, using
>>> sufficient points. Make sure, with Hilbert's help, it's causal.
>>>
>>> 2. Vi(f) = Sum[ Zij(f) x Ij(f) ]. Zij(f) is already on hand from
>>> pkg, pcb model extraction. Here, i= response bump port & j= other bump
>>> ports.
>>> The pcb end (vrm) is @gnd.
>>>
>>> 3. Then Vi(t) = IFFT{Vi(f)} for bump port i. Look, ma ! No
>>> time domain simulation required.
>>>
>>> Please, somebody explain why I never see this in the literature and
>>> major simulator vendors just want to change the subject (for the
>>> most part). Is this a conspiracy? :-) More likely, I'm ignorant of
>>> something.
>>>
>>> Thanks,
>>> Agathon
>>> ----------------------
>>>
>>>
>>>
>
>
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