[SI-LIST] Re: PDN sim: why not IFFT ?
- From: agathon <hreidmarkailen@xxxxxxxxx>
- To: si-list <si-list@xxxxxxxxxxxxx>
- Date: Wed, 17 Jul 2013 18:19:25 -0400
Istvan,
Thanks very much. At least, now I know I'm not down the rabbit hole.
All my models are of passives, including die which is just interconnect,
and so LTI.
You say "...linear and time invariant ..." (LTI) ... Instead, don't you
mean causal for passives models? You have a paper or two on this.
* Also, my stimulus is die side & steady state (enforced) only, dc
suppressed & start is windowed, in the form of a PWL file, extracted from
actual die ckt with std flow. Avg of data record = 0. As a result, I can
read the wc bump noise as simply the neg. peak in the sim result.
* The dc drop is totally separate; handled differently. I don't use a vrm
dc source. I gnd the vrm end, again because I want steady state, in order
to help with the approach taken. My result is die Vnoise (steady state) at
bumps.
* Further, the vrm and all other pcb noise sources I segregate into a
different problem; I'm dealing with die only impact at bumps (with pcb
model included & all pkg/pcb dcaps). The pcb sources can be done in a sep.
sim and added in to the budget (by LTI). It's a different animal
altogether. I don't include any pcb filters for ext. noise, like inductors
or ferrites; they're part of ext. noise filtering.
* Additionally, a vrm dc step does nothing but show how substrates &
passives respond to a the supply's step; irrelevant to me for die bump
considerations. A vrm also introduces big headaches requiring use of
initial conditions to get the sim stable @ that step (even if smooth),
since it by definition injects current ramps as initial operating condition
(V=L*di/dt) that aren't "real" for my simulation. Likewise, any die
current stim ramps induce V steps. Avoiding init conditions and ext. step
sources also means I help avoid the low freq. minefields in models.
* So, I need a huge stimulus length to cover the freq. range and a huge #
of points, but I'm not dealing with the deep low freq of pcb noise sources
here.
* The die stimulus is based on a PRBS just long enough to cover the total
sim time (1-3+ usec). Bad choice to concatenate shorter PRBS; you get
harmonics at the PRBS period. Tradeoff is that the longer PRBS gives you
longer run-lengths, so less hi-freq energy. Looking into causal notch
filter with the concat method to attenuate the harmonics.
Waddya think?
On Tue, Jul 16, 2013 at 9:20 AM, Istvan Novak <istvan.novak@xxxxxxxxxxx>wrote:
> Hello Agathon,
>
> Theoretically there is nothing wrong with the process. Practical details
> may make a
> generic implementation challenging. We need to assume that the entire PDN
> is
> linear and time invariant and in this case (from power source to bump),
> this means
> not only the capacitors and the DC source, but also the silicon. Another
> practical
> challenge is the very wide relative bandwidth: DC sources may have
> signatures
> in the kHz frequency range, the package and silicon have features in the
> GHz
> frequency range. The usual FFT processes require equidistant spacing of
> samples,
> which can result in millions of points to transform. Doable today, but
> just a
> little while back this was a major hurdle. And there is the uncertainty
> of the
> excitation waveform. When people do the same process in signal integrity,
> the
> signal is much better known; with PDN noise generated by the silicon, many
> users
> would be left to wild speculations.
>
> Best regards,
>
> Istvan Novak
> Oracle
>
>
>
> On 7/16/2013 2:33 AM, agathon wrote:
>
>> Hello all,
>> For obtaining a time domain response at IC bumps, V(t), given the die
>> current stimulus I(t) which is already assured to be steady state itself
>> in
>> a single record, not a repeated concatenation with a constant moving avg.,
>> then dc suppressed, the following seems straightforward:
>>
>> 1. Convert stimulus I(t) to the freq. domain with FFT, using sufficient
>> points. Make sure, with Hilbert's help, it's causal.
>>
>> 2. Vi(f) = Sum[ Zij(f) x Ij(f) ]. Zij(f) is already on hand from pkg,
>> pcb model extraction. Here, i= response bump port & j= other bump ports.
>> The pcb end (vrm) is @gnd.
>>
>> 3. Then Vi(t) = IFFT{Vi(f)} for bump port i. Look, ma ! No time
>> domain simulation required.
>>
>> Please, somebody explain why I never see this in the literature and major
>> simulator vendors just want to change the subject (for the most part). Is
>> this a conspiracy? :-) More likely, I'm ignorant of something.
>>
>> Thanks,
>> Agathon
>> ----------------------
>>
>>
>>
>
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