[SI-LIST] Re: PDN design
- From: Michael Greim <mgreim001@xxxxxxxxx>
- To: Jennifer Maharani <jennifer.maharani@xxxxxxxxx>
- Date: Wed, 24 Mar 2010 08:53:53 -0500
Hi Jenni,
In short, no, it is not enough.
Easier for me to prove by example.
1) In an effort to save money a senior engineer changed the
power plane copper weight from 1 oz to 1/2 copper. What
he forgot to consider was that there was a low voltage deca-amp
distribution path that meandered its was around and across
the plane. End result was that the device at the end of the path
ended up with a lower voltage than it could operate with. So,
boost the output of the supply you say? Well, when he tried that
the first load on the rail had a higher voltage than it could operate
with. Lesson learned? Beware of IR drop on low voltage (1.2V in
this case) very high current paths.
2) An ASIC had problems with dropping bits of data under heavy load.
The chip worked properly on many other boards except two new ones.
Looking at the decoupling beneath the chip every thing looked fine.
Unfortunately, no one had looked at what rails the caps were attached
to. In the layout tool by assigning different colors to different
rails it
became painfully obvious that a large number of the caps beneath the
device were attached to power rails that the chip could care less
about.
Hence, the dropping of bits of data occasionally. Someone had
thought
that they had a "better" decoupling scheme than the previous designer.
Lesson learned? Don't just change something without a good reason
and proper checking.
3) I've also fixed a number of designs where the designer deleted
decoupling
caps because "there wasn't room" for them. What they forgot to check
was
if they were needed for the chip to work. They were.
Hope this helps.
-Michael
And all this science they don't understand
Is just my job six days a week.....
We will either find a way or make one -Hannibal
In the middle of every difficulty lies opportunity -Al Einstein
On Wed, Mar 24, 2010 at 8:33 AM, Jennifer Maharani <
jennifer.maharani@xxxxxxxxx> wrote:
> Hello all,
>
> In designing PDN (chip-pkg-board), many people do frequency domain
> analysis to determine the impedance of the PDN. What is it for? As far
> as power integrity is concerned, isn't it better and enough to run
> transient simulation to see the PWR/GND bounce seen from the chip e.g.
> I/O ?
>
> Many thanks,
> Jenni
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--
Best Regards,
Michael C. Greim
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