[SI-LIST] Re: PDN Question
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: Joel Brown <joel@xxxxxxxxxx>
- Date: Wed, 07 Apr 2010 21:19:23 -0400
Hi Joel,
These are the usual dilemmas in many designs.
Just a few quick comments:
- if you need to lower the cumulative inductance from your capacitors,
you can consider
using multiple vias per pad. Downside: with your planes in the middle of
the stack, more
vias will block more routing unless you do backdrilling or sequential
lamination.
- the bottom side of the board is not necessarily useless for
low-inductance PDN.
Consider the case when a consumer has multiple power/ground vias
(typical for FPGA core).
The multiple vias can connect to the surface effectively, so if you had
your power plane
closer to the bottom, it could still be connected with relatively low
inductance to the
package on the top side and you could bypass it with fewer caps on the
bottom.
Alternately you could leave the planes in the middle and see if you can
add bypass
capacitors directly across the power/ground pins on the bottom. This
will depend on
many factors, but it is becoming more widely available.
- your asymmetrical stackup may work well if the board is small or if
the assembly
can live with some warpage. I would not do this on large boards, because
the copper
utilization is very different on signal versus power layers.
Regards,
Istvan Novak
Oracle-Sun
Joel Brown wrote:
> Currently I am using the Altera PDN tool for Stratix III.
> With the values I entered the target impedance is 0.012 ohms.
>
> There is also Feffective of 59 MHz.
>
> The users manual states that using PCB capacitors for PDN
>
> decoupling beyond their effective frequency range brings little improvement
> to PDN
>
> performance and raises the bill of materials (BOM) cost.
>
>
>
> So my first question would be why is it ok to not provide bypassing beyond
> this Feffective frequency?
>
> I do realize that it may not be possible to do this which what I think is
> what Altera is saying.
>
> But what will prevent the noise voltage from exceeding limits above this
> frequency?
>
> I do know that Altera has internal bypass capacitors on these parts but
> there is no information on their characteristics.
>
>
>
> Most of our board designs use power planes in the center of the board.
>
> Here is an example stackup:
>
>
>
> Layer 1: Component side / Signals
>
> Layer 2: Ground Plane
>
> Layer 3: Signal 1
>
> Layer 4: Signal 2
>
> Layer 5: Ground Plane
>
> Layer 6: Power Plane
>
> Layer 7: Power Plane
>
> Layer 8: Ground Plane
>
> Layer 9: Signal 3
>
> Layer 10: Signal 4
>
> Layer 11: Ground Plane
>
> Layer 12: Solder side / Signals
>
>
>
> We do this to reduce layer count and so the split power planes are
> surrounded by solid ground planes.
>
> In trying to achieve 0.012 ohm target impedance out to 59 MHz I found that I
> reached a point of diminishing returns and no matter how many bypass caps I
> used I could not really get there even with X2Y caps. By playing around I
> found that reducing the inductance by moving the power planes closer to the
> top layer I could achieve the target impedance. But this would mean a
> different stackup:
>
>
>
> Layer 1: Component side / Signals
>
> Layer 2: Ground Plane
>
> Layer 3: Power Plane
>
> Layer 4: Power Plane
>
> Layer 5: Ground Plane
>
> Layer 6: Signal 1
>
> Layer 7: Ground Plane
>
> Layer 8: Signal 2
>
> Layer 9: Signal 3
>
> Layer 10: Ground Plane
>
> Layer 11: Signal 4
>
> Layer 12: Ground Plane
>
> Layer 13: Power Plane
>
> Layer 14: Power Plane
>
> Layer 15: Ground Plane
>
> Layer 16: Solder side / Signals
>
>
>
> Now the board has gone from 12 layers to 16 layers and the power planes on
> layers 13 and 14 are of no use for high frequency bypassing.
>
>
>
> My next question would be is it possible to use a slightly asymmetrical
> stack up like this:
>
>
>
> Layer 1: Component side / Signals
>
> Layer 2: Ground Plane
>
> Layer 3: Power Plane
>
> Layer 4: Power Plane
>
> Layer 5: Ground Plane
>
> Layer 6: Signal 1
>
> Layer 7: Signal 2
>
> Layer 8: Ground Plane
>
> Layer 9: Signal 3
>
> Layer 10: Signal 4
>
> Layer 11: Ground Plane
>
> Layer 12: Solder side / Signals
>
>
>
> The copper weight of the power planes would be ½ oz to match Signal layers 9
> and 10.
>
> Would this be manufacturable? Would any special technology be required?
>
> I keep hearing that boards with asymmetrical stack ups will warp too much.
>
>
>
> Thanks – Joel
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
