[SI-LIST] PCIe3 Electrical Compliance Query

From: vinod ah <ah.vinod@xxxxxxxxx>
To: SI-LIST <si-list@xxxxxxxxxxxxx>
Date: Mon, 13 Jan 2014 12:31:45 +0530

Hi All,
I have very specific queries on PCIe 3 electrical tests used for CEM spec
compliance. Below are the same. Can you please help me out here :-)


1) In *PCIe Tx *electrical testing of DUT in compliance mode, we feed a
100MHz burst to Rx pin of DUT. This 100MHz will switch the waveforms
on Tx i.e. Gen1 --> Gen2 3.5dB --> Gen2 6dB --> P0....P10.

I was trying to understand how this 100MHz is handled by the CDR of Rx
DUT as the frequency is too low for the CDR to lock right?



2) In *PCIe3 Rx* electrical testing in loopback mode, we change the
presets out of BERT which is fed to Rx of DUT. But when we calibrate
the eye for CEM spec, we use preset7 and calibrate to 41ps EW and 46mV
EH.
So ideally speaking we should pass BER of 1 in 10^-12 in P7. Why do we
sweep the preset and try to find the passing preset instead of just
testing at P7. Infact i see BER passing at other presets and failing
at P7.
By changing the preset we are changing EH & EW and hence i don't
understand the point why we calibrate the eye at first place?

Regards
Vinod A H


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List forum  is accessible at:
               http://tech.groups.yahoo.com/group/si-list

List archives are viewable at:     
                //www.freelists.org/archives/si-list
 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

[SI-LIST] PCIe3 Electrical Compliance Query

Other related posts: