Boris,
If you are asking how this is addressed in the spec, I think the answer is
that the spec purposely does not address this question. Addressing it
by specifying the common-mode impedance would limit the implementation
choices and addressing it by explaining the various options and trade-offs
would go way beyond the scope of the spec. But to your point, in signaling
standards where differential-mode impedance is specified but common-mode
impedance is not, it would be good to have a sentence or two saying why it
is not specified.
Regards,
Istvan Novak
Oracle
On 10/9/2016 2:51 AM, Boris Bakshan wrote:
Hi,
Thank you for your explanations.
All the above considerations are familiar to me. I am more interested
to know how the PCIe specification addresses this topics since it is
not brought up explicitly in the electrical spec (especially the
common mode impedance).
Thank you again!
On Sat, Oct 8, 2016 at 6:28 PM, Istvan Novak <istvan.novak@xxxxxxxxxxx
<mailto:istvan.novak@xxxxxxxxxxx>> wrote:
Boris,
A few signaling standards have both differential and common-mode
impedances specified, but many dont. This provides the freedom for
the user to set it according to local circumstances. These two
impedances -as you point out- are related to the coupling strength
in the differential pair. If you search the archives, you will
see that
this topic has been debated multiple times, it might be useful to
look through past comments. As a brief summary, in scenarios
where the entire path is on the same board with no or just a few
tight spots to route through and the cross section is relatively
spacious, loosely couple traces are generally preferred and work
better.
On high density boards with big via arrays to route through, more
tightly coupled traces work better. In these days many of the
terminations are provided on the silicon. On the transmit side they
are just single-ended driver impedances. At lower frequencies there
are simple ways to provide correct termination for both modes:
differential clock circuits often have PI or T termination network
that simultaneously provide the correct termination for both modes.
At higher speeds its effectiveness is diminishing because in the
return
loss we have to fight the higher frequency discontinuities and the
static
termination accuracy matters less.
Regards,
Istvan Novak
Oracle
On 10/7/2016 4:24 PM, Boris Bakshan wrote:
Hi experts!
I have a few queries regarding PCIe Gen3/4 channel impedance.
1. If the recommended differential PCB trace impedance is
85ohms, what
should be the common impedance of the traces? if it's 25ohms
then tightly
coupled differential pair is mandatory.
2. In that case, which termination values would be considered
as optimal at
the receiver/transmitter to account for minimum common and
differential
reflections? (assuming we have a single resistor to
power/ground per single
trace)
Thank you,
Boris.
