[SI-LIST] Re: PCIe DCD / Jitter simulation

  • From: "Dmitriev-Zdorov, Vladimir" <vladimir_dmitriev-zdorov@xxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 27 Oct 2009 10:00:24 -0600

Hi Steve,

I was interested in the simulation of DCD and would like to add the following

1. There are at least two different sources/definitions of DCD.

(a) DCD as a clock-related issue
Here, for example, odd and even bits may have slightly different duration, 
regardless of the logical value of those bits. The source of this type of DCD 
is typically non-90 degree phase shift between lower frequency clock signals in 
the transmitter multiplexer. With this type of DCD, a DC level changes when we 
change the polarity of the alternating input data sequence '01010101...' (even 
bits become '0', not '1').
 See e.g. 
http://grouper.ieee.org/groups/802/3/ap/public/channel_adhoc/sawyer_c1_0505.pdf
http://www.et.byu.edu/~tmh27/Reducing%20Duty-Cycle%20Distortion%20through%20Band-Pass%20Filtering.ppt

R. Z. Bhatti, M. Denneau, and Jeff Draper, "2 Gbps SerDes Design Based on IBM 
Cu-11 (130nm) Standard Cell Technology, GLSVLSI'06, April 30-May2, 2006, 
Philadelphia, Pennsylvania, USA

 (b) DCD as a data-dependent pulse width variation (because of the threshold 
shift or unequal PU/PD strength). Here, the duration of pulses of level '1' is 
different from those of level '0'. With this type of DCD, a DC level does not 
change if we flip the polarity of the alternating sequence '01010101...'

http://www.maxim-ic.com/appnotes.cfm/an_pk/1916
http://www.sss-mag.com/pdf/jitteragilent_hancock.pdf
http://www.edn.com/article/CA250810.html
http://www.fiber-optics.info/glossary-d.htm#Duty_Cycle_Distortion_Jitter
http://www.home.agilent.com/upload/cmc_upload/All/07-16-03-ThrivingWorld-HighSpeed-4mb.pdf

Depending on the view, the approach to simulating these phenomena should be 
different. The existing term "DCD" does not explain what is meant.


2. Depending on the choice between two above types, the effect of DCD is seen 
differently on the eye diagram, affecting its form and vertical/horizontal 
size. In both cases, the eye diagram/BER surface/contours are not any more 
vertically symmetric and may have DC offset. DCD (in both ways) is a 
manifestation of the system's non-LTI behavior, if we consider how digital 
input transforms into channel's output. (In contrast, ISI is LTI).

3. Uncorrelated jitter/crosstalk/noise typically do not make vertically 
asymmetric eye at least in a statistical sense or if simulated long enough. I 
heard that some EDA vendors simulate DCD effects by simply adding extra amount 
of jitter when post process the eye. This is at least not accurate. DCD should 
be considered 'as is', in its deterministic way and only with that we can hope 
to predict accurate eye. We have algorithms that can predict worst case input 
digital pattern and eye diagram for both types of DCD. They consider DCD in a 
truly deterministic way.

Vladimir

>steve weir wrote:
>Subject: [SI-LIST] Re: PCIe DCD / Jitter simulation

>Hermann, yes. Nominally I would recommend that you run pattern dependent 
>tests with the exception pattern well isolated.  In this case a train of 
>symmetric 1-0 pulses followed by an asymmetric 1-0.  Then the same thing 
>again, but with an asymmetric 0-1.  This tends to make the measurements 
>easier to isolate.

>Steve
>Hermann Ruckerbauer wrote:
>> Hi Steve,
>>
>> thanks for the response, but I'm not sure if I understand, but I guess
>> you do have the same understanding as I do:
>
>> Different to the Words "Duty Cycle Distortion" which originally was used
> e. g. for a clock pattern with different high and low periods (as
> described by Joseph from LeCroy)  the spec tries to accont for the
> minimum Eye that is caused from different effects:
> - ISI due to Bandwidth limitation in the Transmitter (driver + package)
> - SSO noise caused by Power Delivery
> - X-talk (e. g. from the package)
> - DCD from the internal clock tree
> - maybe even external noise from switching Power supplys
>
> So in this case a simulation with a DCD of 0.1UI with no jitter
> distribution would be enough to simulate. But now it depends on the
> implementation of the DCD in the simulator.
> If e. g. always the first bit is the larger one and the second is the
> smaller one the pattern ideally should run twice in such a way, that
> each bit hits the small eye once.
>
> Please let me know if this is what you ment.
>
> regards
>
> Hermann
>
>
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.eyeknowhow.de
> hermann.ruckerbauer@xxxxxxxxxxxxx
> Veilchenstrasse 1
> 94554 Moos
> Tel.: +49 (0)9938 / 902 083
> Mobile:       +49 (0)176  / 787 787 77
> Fax:  +49 (0)3212 / 121 9008
>
>
>
> steve weir schrieb:
>   
>> Hermann, frequency dependent loss in the signal band will give you
>> pattern dependent distortion, IE DCD.
>>
>> Steve
>> Hermann Ruckerbauer wrote:
>>     
>>> Hello,
>>>
>>> I'm just looking in PCI express gen2 simulations, but do not fully
>>> understand the Spec regarding DCD and Jitter (low and high frequency)
>>> for worst case simulations.
>>>
>>> There is mentioned, that the simulation should be done with 0.1 DCD.
>>> Additionally there are 78ps Dj and 28ps for slewing the eye.
>>>
>>> 0.15UI is the max. High Frequency TX jitter. From this 30ps (0.15UI)
>>> one should include 0.1UI (20ps) as DCD in the simulation.
>>> ==> What is the Jitter distribution, that should be assumed here?
>>> I guess a fixed 0.1UI DCD is not correct. Personally I would use +-
>>> 0.05UI with some gaussian distribution, but I'm not sure if this is the
>>> intension there.
>>> This would reduce the eye size, but still results in a nice symmetric
>>> eye.
>>> So in my understanding this is not really a Duty cylce distortion with
>>> e.g. each even bit short and each odd bit long, but high frequency
>>> jitter e. g. introduced by SSO noise and package x-talk.
>>> ==> Is my understanding correct ?
>>>
>>> Additionally there is a value of 78ps Dj mentioned. not sure if I need
>>> to add this in simulation or data evaluation, or if this is accounted
>>> for by the DCD already.
>>> ==> My understanding is, that this is the max value of the sum of the
>>> 0.1DCD + the Jitter introduced by the channel.
>>> Is this correct, or do I need to add this DJ in addition (in simulation
>>> or data evaluation)?
>>> I can evaluate this, but if I place a Receiver eye mask it should be
>>> enough not to violate the mask, correct ?
>>>
>>>
>>> Finally there is there is the jitter that I need to add in the
>>> dataevaluation by slewing the eye (e. g.  28.9ps for common clock
>>> architecture.
>>> ==> is it OK to expand the eye mask by this number (+-15ps from the
>>> center) ?
>>>
>>> So far i have not seen any documents that describe it in a way that I
>>> would understand it (guess I'm just to stupid).  Maybe somebody can
>>> enlighten me here, or point me to some description.
>>>
>>> Thanks and regards
>>>
>>> Hermann
>>>  
>>>
>>>
>>>
>>> EKH - EyeKnowHow
>>> Hermann Ruckerbauer
>>> www.eyeknowhow.de
>>> hermann.ruckerbauer@xxxxxxxxxxxxx
>>> Veilchenstrasse 1
>>> 94554 Moos
>>> Tel.:    +49 (0)9938 / 902 083
>>> Mobile:    +49 (0)176  / 787 787 77
>>> Fax:    +49 (0)3212 / 121 9008
>>>
>>>
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