[SI-LIST] Re: PCIE GEN3 Tx/Rx Insertion Loss Limit
- From: "Mohanty, Sarada" <Sarada.Mohanty@xxxxxxx>
- To: "balaseven@xxxxxxxxx" <balaseven@xxxxxxxxx>, "signal.integrity2@xxxxxxxxx" <signal.integrity2@xxxxxxxxx>
- Date: Sun, 10 Feb 2013 23:13:20 +0530
Hi Bala ,
You are correct,PCI Gen3 having close insertion loss upto -8dB and return loss
up to 12 dB close to gen 2 PCIe.
PCIe Gen 2 having 720ps delay from controller to Gold finger .Approximated 4.2"
length acceptable from controller to Gold finger,,
Note:As the thumb rule 0.25 to 0.35 dB inherent loss per inch for FR4
microstrip traces at 1.25GHz.
Regards,
Sarada
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of bala
Sent: Sunday, February 10, 2013 11:18 AM
To: signal.integrity2@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx; zhuyuan Liu
Subject: [SI-LIST] Re: PCIE GEN3 Tx/Rx Insertion Loss Limit
Hi,
Gen2 spec says...minimum return loss should be -8db...and insertion loss can be
10 to 11 db...make sure ur gen 3 loss budget is close to gen2..
bala
On Feb 9, 2013 11:05 PM, "Dan" <signal.integrity2@xxxxxxxxx> wrote:
> HI Julia
> is the spec you provded is for add in card? i am looking out for the
> spec for add-in card and not mother board.
>
> -18db return loss seems ok. but can you tell me the limit for
> insertion loss? i hope these numbers are without edge finger included.
>
> Regards
> Dan.
>
>
> On Fri, Feb 8, 2013 at 6:48 PM, zhuyuan Liu <julialiu.si@xxxxxxxxx> wrote:
>
> > Hi Dan,
> >
> > I have seen several presentation use
> >
> > *üMaximum calibration channel of 22dB loss at 4GHz (4.3.4.3.1
> > Calibration
> > Channels)*
> >
> > *ü-18dB return loss compliance channel (4.3.4.1.2 Calibration
> > Channel
> > Characteristics)*
> >
> > I personally use it too. But sometimes even though your channel
> > violate above IL and RL, the channel will still work. You'd better
> > to use eye diagram to make sure.
> >
> > Julia
> >
> > On Feb 8, 2013, at 4:02 PM, Dan <signal.integrity2@xxxxxxxxx> wrote:
> >
> > HI Scott,
> > but in the rev3 spec, insertion loss budget for 8GT/S channel is not
> > mentioned. there are numbers only for 2.5GT/S only in the pdf?
> >
> > any idea what that would be 8GT/S?
> >
> > Thank You
> > Dan
> >
> >
> > On Fri, Feb 8, 2013 at 3:37 PM, Scott McMorrow <scott@xxxxxxxxxxxxx>
> > wrote:
> >
> > Dan
> >
> > I suggest you obtain the spec from PCISig
> >
> > http://www.pcisig.com/specifications/pciexpress/base3/
> >
> > On Fri, Feb 8, 2013 at 6:25 PM, Dan <signal.integrity2@xxxxxxxxx> wrote:
> >
> > HI ALL,
> > I have a PCIE Gen3 board x8, where the Tx have -4db insertion loss &
> -10db
> > return loss at 4GHz. Is this loss number within spec.
> >
> > is the spec same for Rx also?
> >
> > Please help
> >
> > regards
> > Dan
> >
> >
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> > --
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