Hi All, I have been chasing my tail the last two days concerning the PCI V2.2 spec that mentions a slew rate between 1 and 4V/ns as well as current sourcing and sinking. My problem is that when I meet the slew rate spec, my current sourcing/sinking doesn't meet the spec anymore. Likewise, when I meet the sourcing/sinking spec, my slew rate is too fast. The PCI V2.2 spec gives a circuit load for measuring slew rate. However, it does not give a circuit load for measuring the current sourcing/sinking. What sort of load do I need to simulate this? One coworker suggested that, for example, one requirement is that with a VDD of 3.0V, the output needs to source 36mA with 0.9V at the output in the high state, that the buffer needs to have a logic hi input, and with a voltage source of 0.9V sitting on the output, the buffer should be sourcing at least 36mA. I am curious to hear what others do to satisfy these requirements. thanks -------------------------------------------------------------- Karl Fritz Design Engineer vox: 507.538.5466 fritz.karl@xxxxxxxx fax: 507.284.9171 Special Purpose Processor Development Group - Mayo Foundation -------------------------------------------------------------- ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu