[SI-LIST] Re: PCI IO buffer problem?
- From: "Sinha, Snehamay" <snehamay@xxxxxx>
- To: yinhongcheng <yinhc@xxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 4 Sep 2008 08:52:51 -0500
For a IO to be able to withstand, hot plugging, the receiver will need an
additional ESD clamp ckt for CDM protection which may or may not be present in
a standard CMOS receiver.
Snehamay
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of yinhongcheng
Sent: Thursday, September 04, 2008 3:37 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCI IO buffer problem?
Hi, All,
Some vendor or foundry provides special PCI(33Mhz or 66Mhz) IO buffer in
their IO buffer library during ASIC design,but some not.
So I want to know what is the difference between common CMOS logic IO and
special PCI IO, if we can use commom IO buffer replace special PCI buffer
during ASIC design?if do so, what factor (such as Hot-plugging and so on)
should be take into account? thanks!
Best Regards
HongchengYin
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