[SI-LIST] Re: PCB extractor to obtain S parameters

  • From: Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx
  • To: josephk@xxxxxxxxxxx, Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Thu, 7 Aug 2008 11:50:51 +0200

Actually, I have "Allegro PCB SI L" tool. 

-----Message d'origine-----
De : Joseph Kao [mailto:josephk@xxxxxxxxxxx]
Envoyé : jeudi 7 août 2008 11:43
À : Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Objet : RE: [SI-LIST] PCB extractor to obtain S parameters


Dear Sir,

You seem to only need S-parameter extraction feature, if you had Cadence PCB SI 
tool, even L or XL, both of them can be plug into one S-parameter function.

Best Regards,
Joseph Kao 


-----Original Message-----
From: Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx 
[mailto:Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx] 
Sent: Thursday, August 07, 2008 5:37 PM
To: Joseph Kao; Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] PCB extractor to obtain S parameters

Sir, 

Thank you for your answer. I know GXL from Cadence.
This tool is more than just an extractor.
I'm just looking for a module who can just extract S parameters from PCB
parameters.

Alexandre AMEDEO

-----Message d'origine-----
De : Joseph Kao [mailto:josephk@xxxxxxxxxxx]
Envoyé : jeudi 7 août 2008 11:30
À : Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Objet : RE: [SI-LIST] PCB extractor to obtain S parameters


Dear Sir,

Cadence tools (Allegro PCB SI-GXL) has the S-parameter extraction &
simulation function.

Please reference :
http://www.cadence.com/products/pcb/pcb_si/pages/configurations.aspx

Regards,
Joseph Kao in Cadence Taiwan 

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx
Sent: Thursday, August 07, 2008 5:24 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCB extractor to obtain S parameters

Hi all, 

I am looking for all PCB tools who can extract PCB information from Cadence
tools and execute analysis to have S parameters of, for example, a
differential trace.

Thanks and regards, 

Thales Land & Joint System - Colombes

Alexandre AMEDEO
Intégrité du Signal
  

-----Message d'origine-----
De : si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]De la part de Luong Hoang
Envoyé : jeudi 7 août 2008 00:33
À : si-list@xxxxxxxxxxxxx
Objet : [SI-LIST] Signal Integrity position at Juniper Networks


Hi all we're looking to fill some signal integrity positions at Juniper
Networks (Sunnyvale, CA).
If you're interested, you can contact the recruiter through his email at

 

BenW@xxxxxxxxxxx   /  BenW[at]Juniper.net

 

Here is a brief description...

 

System level signal integrity and timing analysis on boards, packages,
ASICs and FPGAs.

 

- Design timing (setup/hold board timing analysis and clock design).

- Simulate and measure board level reflection, xtalk, ground bounce,
power/ground noise.  

- Perform simulations for on-chip SI including core noise modeling, on
chip crosstalk, I/O selection, chip pinout assignment, package selection
and pinout assignment.

- PWB cross-section design/tradeoff, serdes channel analysis.

- Use lab equipment such as oscilloscopes, Time Domain Reflectometers,
Vector Network Analyzers, Spectrum Analyzers.  Good lab debug skills.

- Proficient with HSPICE, Allegro, SiSoft, Speed2K, PowerSI, Ansoft
HFSS.

- Good oral and written communication skills.  Team player, willing to
take on a variety of projects, good listening skills, self motivator.

 

 

 


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