[SI-LIST] Re: PCB extractor to obtain S parameters
- From: "Ferhat Yaldiz" <ferhat.yaldiz@xxxxxxxxxxxxxx>
- To: <Ravinder.Ajmani@xxxxxxxxxxxxxx>
- Date: Mon, 11 Aug 2008 14:07:12 +0300
Hi Ravinder,
Allegro PCB SI can deal with splits or slot, void problems. Using "shield"
and "ANL_MIN_VOID_AREA"
Properties, you can see effects because of impedance discontinuity.
Shield : (in the stackup editor) If shield option is not checked, Allegro
PCB SI accept planes are not
ideal or solid and have multiple planes and it forces to find effects plane
boundaries.
ANL_MIN_VOID_AREA : (minimum void area) For void or slot it is useful.
Allegro calculate void effects
in power layers via transtion. (Via perforations) You can find
"ANL_MIN_VOID_AREA" property in the User
Preferences --> Signal Analysis section.
Maybe you must play "Geometry Window" and "min coupled length".
In my some design, I have to route transmission lines over the voids, slots
and near edge of power plane.
I saw Impedance changing. For example, In slots or void Allegro add high
impedance transmission line according to
other transmission lines. In split planes you know adding capacitor where
you are crossing the split will give more realistic result.
Best Regards,
FERHAT YALDIZ
HARDWARE DESIGN ENG.
TUBITAK-ITI
TURKIYE
_____
From: Ravinder.Ajmani@xxxxxxxxxxxxxx [mailto:Ravinder.Ajmani@xxxxxxxxxxxxxx]
Sent: Friday, August 08, 2008 8:51 PM
To: Ferhat Yaldiz
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: PCB extractor to obtain S parameters
Hi Ferhat,
It is my understanding that Allegro PCB SI uses the Ground/Power planes
specified in the card stackup for signal return, and it assumes them to be
ideal planes, ignoring the plane splits and via perforations. If there is a
special feature for split plane simulation then will you please elaborate on
it.
Thanks.
Regards,
Ravinder Ajmani
Server PCB Development
Hitachi Global Storage Technologies
Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
"Ferhat Yaldiz" <ferhat.yaldiz@xxxxxxxxxxxxxx>
Sent by: si-list-bounce@xxxxxxxxxxxxx
08/08/2008 12:06 AM
To
"'qazi'" <qazi@xxxxxxxxxx>, "'Bill Dempsey'" <bdempsey85@xxxxxxxxx>,
<Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
cc
Subject
[SI-LIST] Re: PCB extractor to obtain S parameters
Hi Qazi,
Allegro PCB SI supports split plane simulation. This is very powerful in
high density boards. I compared results critical nets have split planes and
have ideal planes. As I know, Hyperlynx thinks signal return path is
ideal. (I read it own manual.)
Best Regards,
FERHAT YALDIZ
HARDWARE DESIGN ENG.
TUBITAK - ITI
TURKIYE
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of qazi
Sent: Friday, August 08, 2008 2:26 AM
To: 'Bill Dempsey'; Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: PCB extractor to obtain S parameters
I don't think Hyperlynx or Allegro SI can take split paths into
consideration. Unless they have, of course made a very recent update that I
am not aware of.
-Qazi
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Bill Dempsey
Sent: Thursday, August 07, 2008 1:39 PM
To: Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: PCB extractor to obtain S parameters
Be sure to ask your tool vendor if they assume an ideal return path or if
they consider defective return paths (plane splits). Not all vendors can do
that...
The ones I am aware of that have Allegro plug-ins are:
Applied Wave Research
CST
HFSS
Others?
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of
> Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx
> Sent: Thursday, August 07, 2008 4:24 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] PCB extractor to obtain S parameters
>
> Hi all,
>
> I am looking for all PCB tools who can extract PCB
> information from Cadence tools and execute analysis to have S
> parameters of, for example, a differential trace.
>
> Thanks and regards,
>
> Thales Land & Joint System - Colombes
>
> Alexandre AMEDEO
> Intégrité du Signal
>
>
> -----Message d'origine-----
> De : si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]De la part de Luong
> Hoang Envoyé : jeudi 7 août 2008 00:33 À :
> si-list@xxxxxxxxxxxxx Objet : [SI-LIST] Signal Integrity
> position at Juniper Networks
>
>
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> If you're interested, you can contact the recruiter through
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>
>
>
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>
>
>
> Here is a brief description...
>
>
>
> System level signal integrity and timing analysis on boards,
> packages, ASICs and FPGAs.
>
>
>
> - Design timing (setup/hold board timing analysis and clock design).
>
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> bounce, power/ground noise.
>
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> modeling, on chip crosstalk, I/O selection, chip pinout
> assignment, package selection and pinout assignment.
>
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>
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> Reflectometers, Vector Network Analyzers, Spectrum Analyzers.
> Good lab debug skills.
>
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> Ansoft HFSS.
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> willing to take on a variety of projects, good listening
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>
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