[SI-LIST] Re: PCB extractor to obtain S parameters
- From: "qazi" <qazi@xxxxxxxxxx>
- To: "'Bill Dempsey'" <bdempsey85@xxxxxxxxx>, <Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 7 Aug 2008 16:25:39 -0700
I don't think Hyperlynx or Allegro SI can take split paths into
consideration. Unless they have, of course made a very recent update that I
am not aware of.
-Qazi
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Bill Dempsey
Sent: Thursday, August 07, 2008 1:39 PM
To: Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: PCB extractor to obtain S parameters
Be sure to ask your tool vendor if they assume an ideal return path or if
they consider defective return paths (plane splits). Not all vendors can do
that...
The ones I am aware of that have Allegro plug-ins are:
Applied Wave Research
CST
HFSS
Others?
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of
> Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx
> Sent: Thursday, August 07, 2008 4:24 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] PCB extractor to obtain S parameters
>
> Hi all,
>
> I am looking for all PCB tools who can extract PCB
> information from Cadence tools and execute analysis to have S
> parameters of, for example, a differential trace.
>
> Thanks and regards,
>
> Thales Land & Joint System - Colombes
>
> Alexandre AMEDEO
> Intégrité du Signal
>
>
> -----Message d'origine-----
> De : si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]De la part de Luong
> Hoang Envoyé : jeudi 7 août 2008 00:33 À :
> si-list@xxxxxxxxxxxxx Objet : [SI-LIST] Signal Integrity
> position at Juniper Networks
>
>
> Hi all we're looking to fill some signal integrity positions
> at Juniper Networks (Sunnyvale, CA).
> If you're interested, you can contact the recruiter through
> his email at
>
>
>
> BenW@xxxxxxxxxxx / BenW[at]Juniper.net
>
>
>
> Here is a brief description...
>
>
>
> System level signal integrity and timing analysis on boards,
> packages, ASICs and FPGAs.
>
>
>
> - Design timing (setup/hold board timing analysis and clock design).
>
> - Simulate and measure board level reflection, xtalk, ground
> bounce, power/ground noise.
>
> - Perform simulations for on-chip SI including core noise
> modeling, on chip crosstalk, I/O selection, chip pinout
> assignment, package selection and pinout assignment.
>
> - PWB cross-section design/tradeoff, serdes channel analysis.
>
> - Use lab equipment such as oscilloscopes, Time Domain
> Reflectometers, Vector Network Analyzers, Spectrum Analyzers.
> Good lab debug skills.
>
> - Proficient with HSPICE, Allegro, SiSoft, Speed2K, PowerSI,
> Ansoft HFSS.
>
> - Good oral and written communication skills. Team player,
> willing to take on a variety of projects, good listening
> skills, self motivator.
>
>
>
>
>
>
>
>
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