[SI-LIST] Re: Optimizing differential vias for high speed serdes channels
- From: "Yuan, Chenghao (Bruce)" <Chenghao_Yuan@xxxxxxxxxx>
- To: "joel@xxxxxxxxxx" <joel@xxxxxxxxxx>, SI-List <si-list@xxxxxxxxxxxxx>
- Date: Wed, 26 Mar 2014 17:50:55 +0000
Hi Joel:
Zhen is right. Log onto your Mentor supportnet account, and go to:
http://support.mentor.com/assets/MG576767/RFID_Optimizer/RFID_Optimizer.htm
to get an idea about FastEM, real-time tuning and optimization. We also have a
sample differential via structure with 3 pre-defined tuning variables: ground
via spacing, signal via spacing, anti-pad size to demonstrate how these
geometrical parameters affect via performance.
Bruce
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Mu, Zhen
Sent: Wednesday, March 26, 2014 9:16 AM
To: joel@xxxxxxxxxx; SI-List
Subject: [SI-LIST] Re: Optimizing differential vias for high speed serdes
channels
Hi Joel,
Since you are using HL 3D EM, there is a function in the tool called FastEM
which does exactly what you are looking for. You can contact Mentor Support for
more details...
Regards,
Zhen Mu
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Joel Brown
Sent: Wednesday, March 26, 2014 11:47 AM
To: SI-List
Subject: [SI-LIST] Optimizing differential vias for high speed serdes channels
I have been doing some 3D simulations of differential vias using Hyperlynx.3D
EM solver. I have found in general that using a common antipad and increasing
the size of the antipad improves via performance. I started at 28 mil antipad
and went to 50 mil and at 6 GBPS with 2 sets of visa there was about 1.5 dB
improvement in the eye.
I realize this is due to lowering capacitance between the via and ground thus
improving the impedance matching of the vias. One result I found that was
somewhat surprising is when I removed the pads on the unused layers there was
improvement with the 28 mil antipad but with the 50 mil antipad it got worse. I
am not sure why this happened, perhaps the capacitance got too low making the
impedance too high instead of too low. Or maybe it affected the coupling
between the two vias. I am also sure the spacing between the two vias must be
an important factor affecting the differential impedance just as the spacing
between traces would. Other than trial and error is there a faster easier way
to optimize differential vias including hole size, via spacing and antipad
size? I did Google optimizing differential vias for high speed serdes and
didn't find much helpful.
Thanks for any ideas.
Joel
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