[SI-LIST] Re: Optimizing differential vias for high speed serdes channels
- From: "Lambert Simonovich" <bertsimonovich@xxxxxxxxxx>
- To: <joel@xxxxxxxxxx>, "'SI-List'" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 26 Mar 2014 12:35:34 -0400
Joel,
When you increased the antipad size in your first case, you effectively
reduced the excess capacitance and got a better match for impedance. When
you removed the non-functional pads, you likely have excess inductance now
because you tuned the antipad with the pads attached. You need to re-tune
the antipad to balance the impedance again. You might want to start with a
blog post of mine that I wrote a while back that might help you give some
insight into modeling differential vias. There is also a link to my web site
at the end of that posting that has a white paper with more detail if you
need it.
http://blog.lamsimenterprises.com/2011/03/14/the-poor-mans-pcb-via-modeling-
methodology/
-Bert
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Joel Brown
Sent: March-26-14 11:47 AM
To: SI-List
Subject: [SI-LIST] Optimizing differential vias for high speed serdes
channels
I have been doing some 3D simulations of differential vias using
Hyperlynx.3D EM solver. I have found in general that using a common antipad
and increasing the size of the antipad improves via performance. I started
at 28 mil antipad and went to 50 mil and at 6 GBPS with 2 sets of visa there
was about 1.5 dB improvement in the eye.
I realize this is due to lowering capacitance between the via and ground
thus improving the impedance matching of the vias. One result I found that
was somewhat surprising is when I removed the pads on the unused layers
there was improvement with the 28 mil antipad but with the 50 mil antipad it
got worse. I am not sure why this happened, perhaps the capacitance got too
low making the impedance too high instead of too low. Or maybe it affected
the coupling between the two vias. I am also sure the spacing between the
two vias must be an important factor affecting the differential impedance
just as the spacing between traces would. Other than trial and error is
there a faster easier way to optimize differential vias including hole size,
via spacing and antipad size? I did Google optimizing differential vias for
high speed serdes and didn't find much helpful.
Thanks for any ideas.
Joel
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