[SI-LIST] Open traces: how to analyze
- From: Gaurav MATHUR <gaurav.mathur@xxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 7 Oct 2005 17:02:53 +0530
Hello All,
I have to take out SubLVDS Tx signals from test chip at connector =
(probe one) on the test board. Frequency is quite high around 400MHz.
As the connector end is open ended; So for a correct board design:
1.What all I've to take care??
2.Is there any method to analyze the signals?? =20
In normal course we attach IBIS of receiver and driver and do =
simulations in Hyperlynx. But in this case receiver end is probe =
connector which is open.
Please advice.
Regards,
Gaurav.
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