[SI-LIST] Re: One stitching via or more vias is better for 25Gbps application???

  • From: Bert Simonovich <bertsimonovich@xxxxxxxxxx>
  • To: "lee.home.61@xxxxxxxxx" <lee.home.61@xxxxxxxxx>
  • Date: Mon, 8 Sep 2014 07:54:57 -0400

Here is a DesignCon2013 paper on the effect of nearby gnd via placement on HS 
SE and Diff Signals by:
A. Jaze; B. Archambeault; and S. Connor. 

http://e.ubmelectronics.com/images/DesignCon2014/12-WA2_Paper_EffectofNearbyGroundVia.pdf

Bert Simonovich


> On Sep 8, 2014, at 3:35 AM, Leeyuyun <lee.home.61@xxxxxxxxx> wrote:
> 
> Hi, Steve
> Could you help explain
>> I think that you are considering a high frequency problem in low 
>> frequency terms
> I do not understand "in low frequency terms", could you help clarify it?
> How to roughly evaluate cavity effect when stitching via close to signal vias?
> Any white paper or material to show stitching via effect?
> When I ask two parties to run two kinds of simulation, including only one 
> stitching vias and more stitching vias, the result from two parties is 
> different. One shows only one stitching is better, but another shows more 
> stitching vias better. How do I make decision which one is correct?
> Thank you
> Lee
> 
>> steve weir <weirsi@xxxxxxxxxx> 於 2014/9/8 上午11:57 寫道:
>> 
>> It is neither.  It is a description of the physics.  Real engineering 
>> accounts for pertinent physics.
>> 
>> Best Regards,
>> 
>> 
>> Steve
>>> On 9/7/2014 6:41 PM, leeritchey@xxxxxxxxxxxxx wrote:
>>> This sounds like a bit of supposiition rather than real engineering.
>>> 
>>> Sent from my HTC One™ X, an AT&T 4G LTE smartphone
>>> 
>>> ----- Reply message -----
>>> From: "steve weir" <weirsi@xxxxxxxxxx>
>>> To: "Leeyuyun" <lee.home.61@xxxxxxxxx>
>>> Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
>>> Subject: [SI-LIST] Re: One stitching via or more vias is better for 25Gbps 
>>> application???
>>> Date: Sun, Sep 7, 2014 10:43 AM
>>> 
>>> 
>>> I think that you are considering a high frequency problem in low 
>>> frequency terms.  Stitch vias impact the cavity, and when they are in 
>>> close proximity to signal vias and traces, they affect wave modes near 
>>> those structures.  Thinking about stitch vias and the cavities that they 
>>> traverse as though they are continuations of the TEM path that breaks at 
>>> a Z axis transition is not a good approximation.  The Z axis signal 
>>> transition injects the signal energy into the cavity.  The various 
>>> properties of the cavity:  material, and geometry, including what vias 
>>> stitch the cavity surfaces together and where affects how that signal 
>>> energy propagates through the cavity in all directions.
>>> 
>>> Steve
>>>> On 9/7/2014 5:31 AM, Leeyuyun wrote:
>>>> Hi, Steve
>>>> But IL and RL should depend upon the distance / via pad size of signal via 
>>>> and gnd stitching via
>>>> If only depend on capacitor vsd via, is the return path loop larger to 
>>>> create large inductance?
>>>> Does it fit into 25Gbps application?
>>>> Could you advise what is the benefit of case 1 and case 2?
>>>> Thanks
>>>> Lee
>>>> 
>>>> 
>>>>> steve weir <weirsi@xxxxxxxxxx> 於 2014/9/7 下午6:11 寫道:
>>>>> 
>>>>> The statement is based on the idea that Vss stitching from bypass
>>>>> capacitor Vss vias and IC Vss vias is adequate.  The idea concludes that
>>>>> explicit vias corresponding to signal or signal pair transitions are not
>>>>> necessary.
>>>>> 
>>>>> Steve
>>>>>> On 9/7/2014 2:46 AM, Leeyuyun wrote:
>>>>>> Stitching should be needed when gnd reference plane change
>>>>>> I do not know why you said do not need any stitching vias
>>>>>> I want to clarify my question as below
>>>>>> # means stitching vias, * means signal vias, + means positive signal, - 
>>>>>> means negative signal
>>>>>> 1. Only on stitching vias
>>>>>> +++++++++++++++++*++++++++++
>>>>>>                                   #
>>>>>> --------------------------*----------------
>>>>>> 2. At least two stitching vias
>>>>>>                                  #
>>>>>> ++++++++++++++++*+++++++++++
>>>>>> 
>>>>>> ------------------------*------------------
>>>>>>                                  #
>>>>>> For each structure, what is theory behind? What is your recommendation 
>>>>>> for stitching via structure in the 25Gbps structure?
>>>>>> 
>>>>>>> "Lee " <leeritchey@xxxxxxxxxxxxx> 於 2014/9/7 上午3:17 寫道:
>>>>>>> 
>>>>>>> No stitching vias are needed.  Where did this idea get started?
>>>>>>> 
>>>>>>> -----Original Message----- From: Leeyuyun
>>>>>>> Sent: Saturday, September 06, 2014 4:25 AM
>>>>>>> To: si-list@xxxxxxxxxxxxx
>>>>>>> Cc: lee.home.61@xxxxxxxxx
>>>>>>> Subject: [SI-LIST] One stitching via or more vias is better for 25Gbps 
>>>>>>> application???
>>>>>>> 
>>>>>>> Hi, all
>>>>>>> I am doing 100Gbps (4x25Gps) product now
>>>>>>> How do we put stitching vias when high speed signal change the layer?
>>>>>>> This is a differential pair, which has P and N
>>>>>>> Someone told me that one stitching vias is better because P and N share 
>>>>>>> the common return
>>>>>>> Someone told me that more stitching vias is better because loop 
>>>>>>> inductance could be reduced more
>>>>>>> I am confused which one is better?
>>>>>>> Can anyone help me?
>>>>>>> Thanks, 
>>>>>>> Lee------------------------------------------------------------------
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>>>>> 
>>>>> -- 
>>>>> Steve Weir
>>>>> IPBLOX, LLC
>>>>> 1580 Grand Point Way
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>>>>> 
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>>> 
>>> -- 
>>> Steve Weir
>>> IPBLOX, LLC
>>> 1580 Grand Point Way
>>> MS 34689
>>> Reno, NV  89523-9998
>>> www.ipblox.com
>>> 
>>> (775) 299-4236 Business
>>> (866) 675-4630 Toll-free
>>> (707) 780-1951 Fax
>>> 
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>> 
>> 
>> -- 
>> Steve Weir
>> IPBLOX, LLC 
>> 1580 Grand Point Way
>> MS 34689
>> Reno, NV  89523-9998 
>> www.ipblox.com
>> 
>> (775) 299-4236 Business
>> (866) 675-4630 Toll-free
>> (707) 780-1951 Fax
>> 
>> All contents Copyright (c)2013 IPBLOX, LLC.  All Rights Reserved.
>> This e-mail may contain confidential material.
>> If you are not the intended recipient, please destroy all records
>> and notify the sender.
> 
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