[SI-LIST] Re: One stitching via or more vias is better for 25Gbps application???

  • From: Leeyuyun <lee.home.61@xxxxxxxxx>
  • To: "weirsi@xxxxxxxxxx" <weirsi@xxxxxxxxxx>
  • Date: Sun, 7 Sep 2014 20:31:30 +0800

Hi, Steve
But IL and RL should depend upon the distance / via pad size of signal via and 
gnd stitching via
If only depend on capacitor vsd via, is the return path loop larger to create 
large inductance?
Does it fit into 25Gbps application?
Could you advise what is the benefit of case 1 and case 2?
Thanks
Lee


> steve weir <weirsi@xxxxxxxxxx> 於 2014/9/7 下午6:11 寫道:
> 
> The statement is based on the idea that Vss stitching from bypass 
> capacitor Vss vias and IC Vss vias is adequate.  The idea concludes that 
> explicit vias corresponding to signal or signal pair transitions are not 
> necessary.
> 
> Steve
>> On 9/7/2014 2:46 AM, Leeyuyun wrote:
>> Stitching should be needed when gnd reference plane change
>> I do not know why you said do not need any stitching vias
>> I want to clarify my question as below
>> # means stitching vias, * means signal vias, + means positive signal, - 
>> means negative signal
>> 1. Only on stitching vias
>> +++++++++++++++++*++++++++++
>>                                   #
>> --------------------------*----------------
>> 2. At least two stitching vias
>>                                  #
>> ++++++++++++++++*+++++++++++
>> 
>> ------------------------*------------------
>>                                  #
>> For each structure, what is theory behind? What is your recommendation for 
>> stitching via structure in the 25Gbps structure?
>> 
>>> "Lee " <leeritchey@xxxxxxxxxxxxx> 於 2014/9/7 上午3:17 寫道:
>>> 
>>> No stitching vias are needed.  Where did this idea get started?
>>> 
>>> -----Original Message----- From: Leeyuyun
>>> Sent: Saturday, September 06, 2014 4:25 AM
>>> To: si-list@xxxxxxxxxxxxx
>>> Cc: lee.home.61@xxxxxxxxx
>>> Subject: [SI-LIST] One stitching via or more vias is better for 25Gbps 
>>> application???
>>> 
>>> Hi, all
>>> I am doing 100Gbps (4x25Gps) product now
>>> How do we put stitching vias when high speed signal change the layer?
>>> This is a differential pair, which has P and N
>>> Someone told me that one stitching vias is better because P and N share the 
>>> common return
>>> Someone told me that more stitching vias is better because loop inductance 
>>> could be reduced more
>>> I am confused which one is better?
>>> Can anyone help me?
>>> Thanks, 
>>> Lee------------------------------------------------------------------
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> 
> 
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