[SI-LIST] Re: One last question for Chris & Larry re: Power/D ecoupling
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: "'Larry.Smith@xxxxxxx'" <Larry.Smith@xxxxxxx>,ctwardy@xxxxxxxxxxxxxxxxxx
- Date: Fri, 23 Jan 2004 17:49:58 -0800
Here's a neat trick you can try. Most well designed modern processors have
some kind of energy star, power saving power down mode that can literally go
from deep sleep to full throttle in just a few clock cycles. At >1GHz or
<1ns cycle time, the processor itself is one hack of a fancy function
generator with a few ns timing resolution provided you can have the correct
power testing program that can control the amount of computation (hence
power) it executes. Couple that will a flexible PLL on die and a good
tester, you can search and test your package power all day until you hit the
resonance. It is just a matter of resources (product engineers and tester
time). Most of the well designed high power Si chip should have secret pins
that tap directly into the core power and gnd grids for measurements. In
fact, there were proposals to directly use them to control the DC/DC
regulator feedbacks.
-----Original Message-----
From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
Sent: Thursday, January 22, 2004 10:52 AM
To: ctwardy@xxxxxxxxxxxxxxxxxx
Cc: 'silist'
Subject: [SI-LIST] Re: One last question for Chris & Larry re: Power/D
ecoupling
Craig - It is difficult to know the power supply voltage at the
silicon with accuracy at clock frequencies. Sense probes can be wired
into the chip but there are always questions about where on the chip
to place them, how to route them out and how to measure them when you
get out of the package.
We have had real good results at the PCB level and at the top of the
package by using a 50 Ohm coax probe soldered directly to power and
ground. Measurements from an active probe are usually a little
different. The coax probe has very high bandwidth and the
'unprotected' loop where it is attached is very small. You can
certainly measure something on wires that probe into the silicon but I
am not sure that you can believe the results.
There is usually a relationship between the DC voltage and the maximum
frequency that a processor will run. Alex Waizman from Intel has done
some good work in this area. Most of us believe that noise on top of
the DC voltage will decrease Fmax, but this relationship is probably
frequency dependent and difficult to quantify.
It may be possible to inject noise on low power systems, but for 100W
processors, noise injection is difficult at best.
This is a difficult area which is ripe for technical development. I'd
be interested in comments from others on the list for this topic.
regards,
Larry Smith
Sun Microsystems
Craig Twardy wrote:
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