[SI-LIST] Re: On the use of "dots" for copper balance
- From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- To: "leeritchey@xxxxxxxxxxxxx" <leeritchey@xxxxxxxxxxxxx>, "Charles.Grasso@xxxxxxxxxxxx" <Charles.Grasso@xxxxxxxxxxxx>
- Date: Mon, 3 Nov 2014 22:20:07 +0000
I don't think thieving is just done for plating uniformity. For years, I've
seen vendors put thieving on inner layers and I was told that was for prepreg
thickness consistency and etching uniformity. I'm also told (by PCB experts)
that many (most?) outer layers are now being done with "panel plating" (vs.
"pattern plating" that you're describing), and that nullifies the benefit of
thieving if it was only for plating uniformity. Of course, this is for my
domain, which is server boards. I don't know what processes are commonly used
for cell phones, etc.
To answer the original question, I agree with Lee that the metal is kept far
enough away from any signals to preclude issues (in theory, anyway). Be
especially careful if you have buried microstrip, or a dual stripline design
(as Lee said).
FYI (some terminology):
"panel plate": plate the entire outer layers and then etch the geometries.
Can't be used for the finer (<4mil) geometries, but I'm told it's being used
very often now. Cross-sectioning many boards indicates it is usually being
used (as evidenced by the microstrip profile - curved walls, signs of
undercutting, etc.). Thieving wouldn't make any difference to trace plating
thickness, it would only affect the etching.
"pattern plate": only plate the desired geometries. This was the conventional
technique, and thieving affected plating thickness significantly.
Cross-sectioning of these boards shows the conventional "rectangle on a
trapezoid" profile.
As always, I welcome others' information or data, even if it contradicts my
current understanding.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Lee
Sent: Monday, November 03, 2014 12:25 PM
To: aaditya.kandibanda@xxxxxxxxx; Charles.Grasso@xxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: On the use of "dots" for copper balance
Yes, this is only done on the outside layers of a PCB to even out the copper
distribution so plating in the holes is uniform. The dots are not connected to
anything after etching has been done. As long as they are not on top of traces
in layer 2 or layer n-1 they do no harm.
-----Original Message-----
From: Aaditya K
Sent: Monday, November 03, 2014 10:12 AM
To: Charles.Grasso@xxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: On the use of "dots" for copper balance
Hi,
Is it "Copper Thieving?"
Isn't it applied on only top/bottom layer?
Thanks
Aaditya
On Mon, Nov 3, 2014 at 10:00 AM, Grasso, Charles < Charles.Grasso@xxxxxxxxxxxx>
wrote:
> Hello all,
> Has anyone analyzed the impact of the addition of copper dots (used to
> balance the copper etch on a pwb) on high speed pwbs? The proposal is
> NOT to ground these dots. I can see from an SI standpoint that these
> present a capacitive load that could add unwanted dips in the waveform
> but I cannot imagine an EMI issue..am I wrong?
>
> Are there any presentations I can look at? (A Google search for
> brought up some interesting results!)??
>
> Best Regards
> Charles Grasso
> Compliance Engineer
> Echostar Communications
> (w) 303-706-5467
> (c) 303-204-2974
> (t) 3032042974@xxxxxxxxx
> (e) charles.grasso@xxxxxxxxxxxx
> (e2) chasgrasso@xxxxxxxxx
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> //www.freelists.org/webpage/si-list
>
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>
> List forum is accessible at:
> http://tech.groups.yahoo.com/group/si-list
>
> List archives are viewable at:
> //www.freelists.org/archives/si-list
>
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2015.0.5315 / Virus Database: 4189/8501 - Release Date: 11/03/14
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
