[SI-LIST] Re: On the use of "dots" for copper balance
- From: "Lee " <leeritchey@xxxxxxxxxxxxx>
- To: <aaditya.kandibanda@xxxxxxxxx>, <Charles.Grasso@xxxxxxxxxxxx>
- Date: Mon, 3 Nov 2014 12:25:02 -0800
Yes, this is only done on the outside layers of a PCB to even out the copper
distribution so plating in the holes is uniform. The dots are not connected
to anything after etching has been done. As long as they are not on top of
traces in layer 2 or layer n-1 they do no harm.
-----Original Message-----
From: Aaditya K
Sent: Monday, November 03, 2014 10:12 AM
To: Charles.Grasso@xxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: On the use of "dots" for copper balance
Hi,
Is it "Copper Thieving?"
Isn't it applied on only top/bottom layer?
Thanks
Aaditya
On Mon, Nov 3, 2014 at 10:00 AM, Grasso, Charles <
Charles.Grasso@xxxxxxxxxxxx> wrote:
> Hello all,
> Has anyone analyzed the impact of the addition of copper dots (used to
> balance the copper etch on a pwb) on
> high speed pwbs? The proposal is NOT to ground these dots. I can see
> from an SI standpoint that these present a
> capacitive load that could add unwanted dips in the waveform but I cannot
> imagine an EMI issue..am I wrong?
>
> Are there any presentations I can look at? (A Google search for brought up
> some interesting results!)??
>
> Best Regards
> Charles Grasso
> Compliance Engineer
> Echostar Communications
> (w) 303-706-5467
> (c) 303-204-2974
> (t) 3032042974@xxxxxxxxx
> (e) charles.grasso@xxxxxxxxxxxx
> (e2) chasgrasso@xxxxxxxxx
>
>
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