[SI-LIST] Re: On resistance of the driver and the input capacitance of receiver

  • From: "Kelli Caldwell" <kcaldwell@xxxxxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 11 Aug 2003 15:07:36 -0700

Hey Chris,

I hope you're doing well there! I just saw your name and thought I would =
say hello...

Take care,

Kelli

-----Original Message-----
From: Christopher Jakubiec [mailto:Christopher.Jakubiec@xxxxxxx]
Sent: Monday, August 11, 2003 3:05 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: On resistance of the driver and the input
capacitance of receiver


Haritha,

This generally is a question that you would pose to your SPICE modelling =
group,=20
or the foundary that is manufacturing your silicon.  The on resistance =
and input=20
capacitance (gate capacitance) are process specific and depend on =
multiple=20
variables including gate dimension, oxide thickness/type, and doping =
profiles. =20
When I worked on bringing up a 0.13um technology using TSMC as a =
foundary, they=20
provided these types of variables in their SPICE model documentation.

thanks,

Chris Jakubiec
Sun Microsystems


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> Date: Mon, 11 Aug 2003 21:48:20 -0000
> From: "chandaharitha" <chandaharitha@xxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] On resistance of the driver and the input =
capacitance of=20
receiver
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>=20
> Hi
>=20
> If I have a minimum size inverter as both driver and receiver, then
> how should I proceed calculating the on resistance of the driver and
> the input capacitance of the receiver for 0.13um technology.
>=20
> Can you provide the detail documentation on this?
>=20
> Thanks
> Haritha
>=20
>=20
>=20
>=20
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