[SI-LIST] Re: On a different note ....Static Timing with a couple of additional comments
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: twesterh@xxxxxxxxx
- Date: Fri, 24 Sep 2004 11:36:09 -0400
Todd
As a disclaimer, these opinions about to be expressed are my opinions
alone and not the opinions of my employer, Teraspeed. They are based
upon personal experience with each of the tools mentioned, although
limited in some cases, I might add. In addtion, I should disclose that
I am not currently the owner of any of these tools, save Synopsys Hspice
and Excel. However, in the distant past, I have consulted for Mentor and
prior to that Interconnectix, the originator of the ICX tool. (which
places me in the position of knowing a fraction as much about that
software as Weston Beal.) In addition, I am reviewing these tools with
respect to their timing analysis ability and not for other simulations
or usability aspects.
I'd rate the timing methodology of various methods in the following ways:
Most accurate- (but requires expertise in Spice simulation and timing
measurement extraction.)
Spice buffer to buffer simulations with custom timing checks
performed from input of the driven buffer to the output of the receiving
buffer, and measurement data exported to Excel Spreadsheets or Timing
Designer.. This works only if you have design control over both parts
in the driver/receiver link, and only if the methodology for doing chip
timing allows for specification at these internal nodes of the device.
It is costly in terms of time, requires extensive knowledge and external
measurement extraction and post-processing scripts, and can be error
prone. But, this method will always work for any buffer current or future.
Even more accurate (additionally requires significant knowledge of
power/ground modeling)
Spice buffer to buffer simulations, integrated with package
Power/Ground simulations, with custom timing checks performed from input
of the driven buffer to the output of the receiving buffer.
Reasonable to high accuracy at silicon level, with broadest integration
SiSoft Quantum SI, which performs what they call Core-to-Core
simulation from driver to receiver. This software is a repackage of SI
Auditor, with some much needed additions and a much better user
interface. Simulation can be performed with either native Spice I/O
models at high accuracy, or with IBIS models and lower accuracy. This
is a very flexible tool which can be used in Spice or IBIS modeling
modes, and allows for the user to use to integrate package models and
connector models into the modeling flow. At the basic IBIS simulation
level the integration is quite good and the interfaces are reasonably
user friendly. For the advanced user it is possible to perform complex
Spice simulations (as above) with some assistance in connecting of
complex model chains. Where Quantum SI shines is in it's automated
timing measurement and extraction and timing corner generation
capability. All timing measurements and post processing is output
directly into customized Excel spreadsheets. What I am not sure about is
whether the software will perform timing measurements at the input to
output buffers and output of input buffers as can be done in semi-custom
simulation environments, as advocated by Chris Cheng. What really makes
this tool shine is their generalized timing measurement methodology
which automates all currently defined IBIS measurement points (along
with additional custom measurements) and the ability to measure timing
across an arbitrary number of bits in a strobe or data stream for
comprehensive Eye margin processing. No other tool that I know of can do
this today.
Best user interface for board level timing
Mentor ICX has the best user interface for timing setup and
measurements. In addition, it is fairly trivial to export all timing
measurements in a format compatible with spreadsheets. The tool have
very good timing corner case simulation support, however the user is
responsible for running the different corner cases seperately and
integrating the timing data from the various runs. Mentor Tau is an
adjacent tool, which can be used in conjunction with ICX and extract ICX
timing measurements. It is a unique timing tool, which uses a state
dependent approach for timing checks which eliminates false paths.
Unfortunately, it can be a bit daunting to develop timing models for
devices originally. But once they are developed it is a very powerful
and flexible timing analysis tool. Fortunately, both tools can be
script driven, allowing for some very advanced integrated SI and timing
analysis capability, through the use of external programs. In the past,
I've automated tasks such as: typ/min/max IBIS to Spice buffer model
comparisons; multi-board simulation of DDR memory systems with multiple
module types and stuffing options; and worst case timing and SI
simulations of whole boards across min/typ/max voltage, temperature and
process conditions, with integration of the results into one
comprehensive spreadsheet.
Next best user interface
Cadence SpecctraQuest has the next best user interface for an IBIS
simulation tool, in my opinion. Simulation and timing measurement
capabilities are on-par with ICX. However, I find the UI a bit "clunky"
and much too dependent upon the mouse. In addition, there is no
reasonable ability to script repetitive operations, which makes the tool
a bit more cumbersome when setting up a comprehensive timing process
flow. I am not an expert in SpecctraQuest timing measurement and post
processing capabilities, and will let others comments on this aspect of
the tool. Personally, I just find it like driving a stick shift without
synchronizers. Others may have a differing opinion, but if you are
using an Allegro layout environment, it is a no-brainer as the first
tool to begin looking at.
Not yet ready for timing
Mentor Hyperlynx has progressed in it's capabilities since it's
inception many years ago. It is now a formidable and accurate tool,
with equivalent simulation accuracy to ICX and SpecctraQuest. Being a
native IBIS simulation tool, it is extremely fast, and easy for the
beginner to spin up and perform useful simulation. But, because it has
morphed over the years, there is little consistency to the user
interface and methods used. For compehensive board timing, Hyperlynx is
not currently in the same league as the other tools, however, I
understand that major changes are underway. In the near term I believe
some reasonable board level timing support will be provided, and in the
long term, never count out the Hyperlynx team. They have some extremely
talent developers who will most certainly upgrade the tool's timing
capabilites in quick time.
I'm sure this will spark no end in discussion.
scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
(503) 750-6481 Cellular
http://www.teraspeed.com
Teraspeed is the registered service mark of
Teraspeed Consulting Group LLC
Todd Westerhoff (twesterh) wrote:
>What techniques are people using to combine the results of static timing and
>signal integrity analysis for closing timing at the board/system level?
>
>This is a question I've asked a few times before, usually with mixed
>responses. Because the choices for board-level static timing tools are
>relatively few, I'm curious as to which tools are used productively, and
>how.
>
>Replies on and off the list are welcome.
>
>Thanks,
>
>Todd.
>
>Todd Westerhoff
>High Speed Design Specialist
>Cisco Systems
>1414 Massachusetts Ave - Boxboro, MA - 01719
>email:twesterh@xxxxxxxxx
>ph: 978-936-2149
>============================================
>
>"Always do right.
> This will gratify some people and astonish the rest."
>
>- Mark Twain
>
>
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--
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
(503) 750-6481 Cellular
http://www.teraspeed.com
Teraspeed is the registered service mark of
Teraspeed Consulting Group LLC
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