[SI-LIST] Re: On a different note ....
- From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
- To: steve weir <weirsp@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Fri, 24 Sep 2004 06:55:31 -0700
yep - I agree with you in general, regarding home-grown tools.
The excel approach to board level timing is simple and elegant - we dedicate
a page to device timing, a page to trace timing, and then a page to each
interface analyzed. We've found that it's easy to understand (you can past
in timing diagrams, show the equations, and add notes to help understand
each of the interfaces) and it's nice to have everything in one model. We've
been using it for around 4 years now and there are so many positives that
the EDA vendor tool that wants to compete will have a tough sell. But that
said, there are some out there that have some potential - I believe Mentor's
TAU is one of them.
I mentioned there are some weaknesses to our approach. It's cumbersome for
us to break down a bus to the individual signal level : when we give a
min/max it's at the bus level. the challenge is, say on a hold time issue,
that the signal whose trace has the quickest settling time on the bus,
doesn't have the quickest Tco(min) at the chip, so we're overly
conservative. It's cumbersome for our approach to break this down, we can do
it but it becomes complicated, and harder to understand and maintain.
This is where the EDA tools that I've seen are more efficient.
best regards,
Jim
-----Original Message-----
From: steve weir [mailto:weirsp@xxxxxxxxxx]
Sent: Friday, September 24, 2004 7:51 AM
To: james.f.peterson@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: On a different note ....
Jim, one of the values that a vendor tool brings is that it doesn't load
down the organization with the task of maintaining and training people on
custom in-house tools. In larger organizations, vendor tools even if
pricey may pay back easily in terms of the scarce engineering resources
that they save from non-core tasks. OTOH, some amount of in-house tools
can provide an edge in cost or productivity, so mileage will definitely
vary.
Regards,
Steve.
At 04:23 AM 9/24/2004 -0700, Peterson, James F (FL51) wrote:
>Todd,
>without going into too much detail, an excel spreadsheet can be awesome for
>developing (allocating and budgeting timing) and maintaining
>(back-annotating with actual timing) a board-level timing model (see my
>earlier reply in archives). there are some weaknesses in this approach that
>an EDA vendor can fix by creating/selling a custom tool, but I'm currently
>developing one for a board that has DDR SDRAM, QDR SRAM, and RapidIO with
>LVDS, SSTL and HSTL data rates at 250MHz, and it still works.
>best regards,
>Jim Peterson
>Honeywell
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Todd Westerhoff
>(twesterh)
>Sent: Thursday, September 23, 2004 4:17 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] On a different note ....
>
>
>What techniques are people using to combine the results of static timing
and
>signal integrity analysis for closing timing at the board/system level?
>
>This is a question I've asked a few times before, usually with mixed
>responses. Because the choices for board-level static timing tools are
>relatively few, I'm curious as to which tools are used productively, and
>how.
>
>Replies on and off the list are welcome.
>
>Thanks,
>
>Todd.
>
>Todd Westerhoff
>High Speed Design Specialist
>Cisco Systems
>1414 Massachusetts Ave - Boxboro, MA - 01719
>email:twesterh@xxxxxxxxx
>ph: 978-936-2149
>============================================
>
>"Always do right.
> This will gratify some people and astonish the rest."
>
>- Mark Twain
>
>
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