[SI-LIST] Re: On a different note ....
- From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
- To: jonpowell@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 4 Oct 2004 03:29:50 -0700
The way I account for clock convergence in a spreadsheet is exactly how PCI
does it : It's skew and it always hurts you - in other words it's subtracted
in both the setup and hold time equations.
So, if we have two synchronous chips interfacing w/ each other, the skew
between them is another equation that has several components : jitter,
routing, clk buffer skew..... The results are then used in the board's setup
/ hold time equations.
This skew does not include any insertion delay of an asic or fpga. That is
accounted for in a different way.
best regards.
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ray Anderson
Sent: Sunday, October 03, 2004 1:51 PM
To: jonpowell@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: On a different note ....
Jon Powell wrote:
>
>
>How do you handle clock re-convergence with a spread sheet?
>(Or is that no longer a consideration in most digital systems with
>source synchronous clocking).
>
>jon
>
>
>
>
>
Jon-
Not a spreadsheet app, but you might want to check out the program
available from U of Wisc. at the following URL:
http://homepages.cae.wisc.edu/~jltsai/CTune/
Can't vouch for it one way or another as clock convergence and such
isn't really my area of expertise. Perhaps those in the know can comment.
-Ray
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