[SI-LIST] Obscure IBIS model info (was Common Clock and Source Synchronous Timing Margins)
- From: Itzhak Hirshtal <hirshtal@xxxxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 31 Jan 2002 15:48:44 +0200
Hello all,
Since no one has answered my question below, I assume it was not specific
enough. I will now
give all the details needed, and hope someone will have something for me.
The vendor, which I had mentioned below, gave me the following response for my
request for a
description/definition of his test load (Rref, Cref, Vref):
>>
>> Cref
>>
>> High speed output
>>
>> Csocket = 2pf
>> Tx line characteristics are 50 ohm with 2 ns delay.
>>
>> So, Ctxline = 2ns/50 = 40 pf
>> Clump at tester is 10 pf
>> So, Cref = 2+10+40 = 52 pf.
>>
>> Other output
>>
>> Cref - 40 pf to 100 pf
>>
>> Rref and Vref
>>
>> Rref - 50 ohm programmable to adjust the current load.
>> Vref - depending on type of output, you have to select different Vref
>> TTL output - Program the current load such that if the output
>> voltage is above 1.4V then 8ma is drawn out of the output and if the
>> output
>> is below 1.4V then 2ma is forced into the output.
>>
Now, the high speed outputs mentioned in the response are not the focus of my
concern, but the
TTL outputs (app. 60MHz) are.
Can anyone make something of this response?
I myself concluded that I should approximate the current loads mentioned by the
vendor like
this: I assumed "above 1.4V" to be 2.0V, and "below 1.4V" to be 0.8V. Then I
wrote 2 equations
(for the currents that would flow through the resistor) with 2 unknowns (Vref
and Rref) and
thus got to Vref=1.0V and Rref=100ohm.
For Cref I just took 50pf, because it is between 40pf and 100pf and because the
vendor gives
this value to his spec for the rise time of the signals. Anyway, how one should
interpret the
40-100pf range?
Even a hint will help, thanks
Itzhak Hirshtal wrote:
> I encountered a manufacturer who
> claimed he used a current-source test load, with a different current load for
> the high and
> low states of the tested outputs. I had to use approximations in order to be
> able to
> simulate these outputs using an IBIS model. Has anyone encountered such a
> problem and have
> a solution?
Itzhak Hirshtal - Elta Electronics
POB 330 Ashdod Israel 77102
Tel : 972-8-8572841
Mobile: 972-64-238631
Fax : 972-8-8572978
email: hirshtal@xxxxxxxxxxxxx
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